openMSX
MSXCPU.cc
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1 #include "MSXCPU.hh"
2 #include "MSXMotherBoard.hh"
3 #include "Debugger.hh"
4 #include "Scheduler.hh"
5 #include "SimpleDebuggable.hh"
6 #include "BooleanSetting.hh"
7 #include "IntegerSetting.hh"
8 #include "TclCallback.hh"
9 #include "CPUCore.hh"
10 #include "Z80.hh"
11 #include "R800.hh"
12 #include "InfoTopic.hh"
13 #include "TclObject.hh"
14 #include "serialize.hh"
15 #include "unreachable.hh"
16 #include "memory.hh"
17 #include <cassert>
18 
19 using std::string;
20 using std::vector;
21 
22 namespace openmsx {
23 
24 class TimeInfoTopic final : public InfoTopic
25 {
26 public:
27  TimeInfoTopic(InfoCommand& machineInfoCommand,
28  MSXCPU& msxcpu);
29  void execute(array_ref<TclObject> tokens,
30  TclObject& result) const override;
31  string help (const vector<string>& tokens) const override;
32 private:
33  MSXCPU& msxcpu;
34 };
35 
36 class CPUFreqInfoTopic final : public InfoTopic
37 {
38 public:
39  CPUFreqInfoTopic(InfoCommand& machineInfoCommand,
40  const string& name, CPUClock& clock);
41  void execute(array_ref<TclObject> tokens,
42  TclObject& result) const override;
43  string help (const vector<string>& tokens) const override;
44 private:
45  CPUClock& clock;
46 };
47 
48 class MSXCPUDebuggable final : public SimpleDebuggable
49 {
50 public:
51  MSXCPUDebuggable(MSXMotherBoard& motherboard, MSXCPU& cpu);
52  byte read(unsigned address) override;
53  void write(unsigned address, byte value) override;
54 private:
55  MSXCPU& cpu;
56 };
57 
58 
60  : motherboard(motherboard_)
61  , traceSetting(make_unique<BooleanSetting>(
62  motherboard.getCommandController(), "cputrace",
63  "CPU tracing on/off", false, Setting::DONT_SAVE))
64  , diHaltCallback(make_unique<TclCallback>(
65  motherboard.getCommandController(), "di_halt_callback",
66  "Tcl proc called when the CPU executed a DI/HALT sequence"))
67  , z80(make_unique<CPUCore<Z80TYPE>>(
68  motherboard, "z80", *traceSetting,
69  *diHaltCallback, EmuTime::zero))
70  , r800(motherboard.isTurboR()
72  motherboard, "r800", *traceSetting,
73  *diHaltCallback, EmuTime::zero)
74  : nullptr)
75  , timeInfo(make_unique<TimeInfoTopic>(
76  motherboard.getMachineInfoCommand(), *this))
77  , z80FreqInfo(make_unique<CPUFreqInfoTopic>(
78  motherboard.getMachineInfoCommand(), "z80_freq", *z80))
79  , r800FreqInfo(r800
81  motherboard.getMachineInfoCommand(), "r800_freq", *r800)
82  : nullptr)
83  , debuggable(make_unique<MSXCPUDebuggable>(motherboard_, *this))
84  , reference(EmuTime::zero)
85 {
86  z80Active = true; // setActiveCPU(CPU_Z80);
87  newZ80Active = z80Active;
88 
89  motherboard.getDebugger().setCPU(this);
90  motherboard.getScheduler().setCPU(this);
91  traceSetting->attach(*this);
92 
93  z80->freqLocked->attach(*this);
94  z80->freqValue->attach(*this);
95  if (r800) {
96  r800->freqLocked->attach(*this);
97  r800->freqValue->attach(*this);
98  }
99 }
100 
102 {
103  traceSetting->detach(*this);
104  z80->freqLocked->detach(*this);
105  z80->freqValue->detach(*this);
106  if (r800) {
107  r800->freqLocked->detach(*this);
108  r800->freqValue->detach(*this);
109  }
110  motherboard.getScheduler().setCPU(nullptr);
111  motherboard.getDebugger() .setCPU(nullptr);
112 }
113 
115 {
116  z80 ->setInterface(interface);
117  if (r800) r800->setInterface(interface);
118 }
119 
121 {
122  z80 ->doReset(time);
123  if (r800) r800->doReset(time);
124 
125  reference = time;
126 }
127 
129 {
130  if (cpu == CPU_R800) assert(r800);
131 
132  bool tmp = cpu == CPU_Z80;
133  if (tmp != z80Active) {
134  exitCPULoopSync();
135  newZ80Active = tmp;
136  }
137 }
138 
139 void MSXCPU::setDRAMmode(bool dram)
140 {
141  assert(r800);
142  r800->setDRAMmode(dram);
143 }
144 
145 void MSXCPU::execute(bool fastForward)
146 {
147  if (z80Active != newZ80Active) {
148  EmuTime time = getCurrentTime();
149  z80Active = newZ80Active;
150  z80Active ? z80 ->warp(time)
151  : r800->warp(time);
152  invalidateMemCache(0x0000, 0x10000);
153  }
154  z80Active ? z80 ->execute(fastForward)
155  : r800->execute(fastForward);
156 }
157 
159 {
160  z80Active ? z80 ->exitCPULoopSync()
161  : r800->exitCPULoopSync();
162 }
164 {
165  z80Active ? z80 ->exitCPULoopAsync()
166  : r800->exitCPULoopAsync();
167 }
168 
169 EmuTime::param MSXCPU::getCurrentTime() const
170 {
171  return z80Active ? z80 ->getCurrentTime()
172  : r800->getCurrentTime();
173 }
174 
176 {
177  z80Active ? z80 ->setNextSyncPoint(time)
178  : r800->setNextSyncPoint(time);
179 }
180 
181 void MSXCPU::updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
182 {
183  invalidateMemCache(page * 0x4000, 0x4000);
184  if (r800) r800->updateVisiblePage(page, primarySlot, secondarySlot);
185 }
186 
187 void MSXCPU::invalidateMemCache(word start, unsigned size)
188 {
189  z80Active ? z80 ->invalidateMemCache(start, size)
190  : r800->invalidateMemCache(start, size);
191 }
192 
194 {
195  z80 ->raiseIRQ();
196  if (r800) r800->raiseIRQ();
197 }
199 {
200  z80 ->lowerIRQ();
201  if (r800) r800->lowerIRQ();
202 }
204 {
205  z80 ->raiseNMI();
206  if (r800) r800->raiseNMI();
207 }
209 {
210  z80 ->lowerNMI();
211  if (r800) r800->lowerNMI();
212 }
213 
214 bool MSXCPU::isM1Cycle(unsigned address) const
215 {
216  return z80Active ? z80 ->isM1Cycle(address)
217  : r800->isM1Cycle(address);
218 }
219 
220 void MSXCPU::setZ80Freq(unsigned freq)
221 {
222  z80->setFreq(freq);
223 }
224 
226 {
227  z80Active ? z80 ->wait(time)
228  : r800->wait(time);
229 }
230 
231 void MSXCPU::waitCycles(unsigned cycles)
232 {
233  z80Active ? z80 ->waitCycles(cycles)
234  : r800->waitCycles(cycles);
235 }
236 
237 void MSXCPU::waitCyclesR800(unsigned cycles)
238 {
239  if (isR800Active()) {
240  r800->waitCycles(cycles);
241  }
242 }
243 
245 {
246  if (z80Active) {
247  return *z80;
248  } else {
249  return *r800;
250  }
251 }
252 
253 void MSXCPU::update(const Setting& setting)
254 {
255  z80 ->update(setting);
256  if (r800) r800->update(setting);
257  exitCPULoopSync();
258 }
259 
260 // Command
261 
263  Interpreter& interp, array_ref<TclObject> tokens,
264  TclObject& result) const
265 {
266  z80Active ? z80 ->disasmCommand(interp, tokens, result)
267  : r800->disasmCommand(interp, tokens, result);
268 }
269 
270 void MSXCPU::setPaused(bool paused)
271 {
272  if (z80Active) {
273  z80 ->setExtHALT(paused);
274  z80 ->exitCPULoopSync();
275  } else {
276  r800->setExtHALT(paused);
277  r800->exitCPULoopSync();
278  }
279 }
280 
281 
282 // class TimeInfoTopic
283 
285  MSXCPU& msxcpu_)
286  : InfoTopic(machineInfoCommand, "time")
287  , msxcpu(msxcpu_)
288 {
289 }
290 
292  TclObject& result) const
293 {
294  EmuDuration dur = msxcpu.getCurrentTime() - msxcpu.reference;
295  result.setDouble(dur.toDouble());
296 }
297 
298 string TimeInfoTopic::help(const vector<string>& /*tokens*/) const
299 {
300  return "Prints the time in seconds that the MSX is powered on\n";
301 }
302 
303 
304 // class CPUFreqInfoTopic
305 
307  const string& name, CPUClock& clock_)
308  : InfoTopic(machineInfoCommand, name)
309  , clock(clock_)
310 {
311 }
312 
314  TclObject& result) const
315 {
316  result.setInt(clock.getFreq());
317 }
318 
319 string CPUFreqInfoTopic::help(const vector<string>& /*tokens*/) const
320 {
321  return "Returns the actual frequency of this CPU.\n"
322  "This frequency can vary because:\n"
323  " - the user has overridden the freq via the '{z80,r800}_freq' setting\n"
324  " - (only on some MSX machines) the MSX software can switch the Z80 between 2 frequencies\n"
325  "See also the '{z80,r800}_freq_locked' setting.\n";
326 }
327 
328 
329 // class MSXCPUDebuggable
330 
331 static const char* const CPU_REGS_DESC =
332  "Registers of the active CPU (Z80 or R800).\n"
333  "Each byte in this debuggable represents one 8 bit register:\n"
334  " 0 -> A 1 -> F 2 -> B 3 -> C\n"
335  " 4 -> D 5 -> E 6 -> H 7 -> L\n"
336  " 8 -> A' 9 -> F' 10 -> B' 11 -> C'\n"
337  " 12 -> D' 13 -> E' 14 -> H' 15 -> L'\n"
338  " 16 -> IXH 17 -> IXL 18 -> IYH 19 -> IYL\n"
339  " 20 -> PCH 21 -> PCL 22 -> SPH 23 -> SPL\n"
340  " 24 -> I 25 -> R 26 -> IM 27 -> IFF1/2\n"
341  "The last position (27) contains the IFF1 and IFF2 flags in respectively\n"
342  "bit 0 and 1. Bit 2 contains 'IFF1 AND last-instruction-was-not-EI', so\n"
343  "this effectively indicates that the CPU could accept an interrupt at\n"
344  "the start of the current instruction.\n";
345 
347  : SimpleDebuggable(motherboard, "CPU regs", CPU_REGS_DESC, 28)
348  , cpu(cpu_)
349 {
350 }
351 
352 byte MSXCPUDebuggable::read(unsigned address)
353 {
354  const CPURegs& regs = cpu.getRegisters();
355  switch (address) {
356  case 0: return regs.getA();
357  case 1: return regs.getF();
358  case 2: return regs.getB();
359  case 3: return regs.getC();
360  case 4: return regs.getD();
361  case 5: return regs.getE();
362  case 6: return regs.getH();
363  case 7: return regs.getL();
364  case 8: return regs.getA2();
365  case 9: return regs.getF2();
366  case 10: return regs.getB2();
367  case 11: return regs.getC2();
368  case 12: return regs.getD2();
369  case 13: return regs.getE2();
370  case 14: return regs.getH2();
371  case 15: return regs.getL2();
372  case 16: return regs.getIXh();
373  case 17: return regs.getIXl();
374  case 18: return regs.getIYh();
375  case 19: return regs.getIYl();
376  case 20: return regs.getPCh();
377  case 21: return regs.getPCl();
378  case 22: return regs.getSPh();
379  case 23: return regs.getSPl();
380  case 24: return regs.getI();
381  case 25: return regs.getR();
382  case 26: return regs.getIM();
383  case 27: return 1 * regs.getIFF1() +
384  2 * regs.getIFF2() +
385  4 * (regs.getIFF1() && !regs.debugGetAfterEI());
386  default: UNREACHABLE; return 0;
387  }
388 }
389 
390 void MSXCPUDebuggable::write(unsigned address, byte value)
391 {
392  CPURegs& regs = cpu.getRegisters();
393  switch (address) {
394  case 0: regs.setA(value); break;
395  case 1: regs.setF(value); break;
396  case 2: regs.setB(value); break;
397  case 3: regs.setC(value); break;
398  case 4: regs.setD(value); break;
399  case 5: regs.setE(value); break;
400  case 6: regs.setH(value); break;
401  case 7: regs.setL(value); break;
402  case 8: regs.setA2(value); break;
403  case 9: regs.setF2(value); break;
404  case 10: regs.setB2(value); break;
405  case 11: regs.setC2(value); break;
406  case 12: regs.setD2(value); break;
407  case 13: regs.setE2(value); break;
408  case 14: regs.setH2(value); break;
409  case 15: regs.setL2(value); break;
410  case 16: regs.setIXh(value); break;
411  case 17: regs.setIXl(value); break;
412  case 18: regs.setIYh(value); break;
413  case 19: regs.setIYl(value); break;
414  case 20: regs.setPCh(value); break;
415  case 21: regs.setPCl(value); break;
416  case 22: regs.setSPh(value); break;
417  case 23: regs.setSPl(value); break;
418  case 24: regs.setI(value); break;
419  case 25: regs.setR(value); break;
420  case 26:
421  if (value < 3) regs.setIM(value);
422  break;
423  case 27:
424  regs.setIFF1((value & 0x01) != 0);
425  regs.setIFF2((value & 0x02) != 0);
426  // can't change afterEI
427  break;
428  default:
429  UNREACHABLE;
430  }
431 }
432 
433 // version 1: initial version
434 // version 2: activeCPU,newCPU -> z80Active,newZ80Active
435 template<typename Archive>
436 void MSXCPU::serialize(Archive& ar, unsigned version)
437 {
438  if (ar.versionAtLeast(version, 2)) {
439  ar.serialize("z80", *z80);
440  if (r800) ar.serialize("r800", *r800);
441  ar.serialize("z80Active", z80Active);
442  ar.serialize("newZ80Active", newZ80Active);
443  } else {
444  // backwards-compatibility
445  assert(ar.isLoader());
446 
447  ar.serializeWithID("z80", *z80);
448  if (r800) ar.serializeWithID("r800", *r800);
449  CPUBase* activeCPU = nullptr;
450  CPUBase* newCPU = nullptr;
451  ar.serializePointerID("activeCPU", activeCPU);
452  ar.serializePointerID("newCPU", newCPU);
453  z80Active = activeCPU == z80.get();
454  if (newCPU) {
455  newZ80Active = newCPU == z80.get();
456  } else {
457  newZ80Active = z80Active;
458  }
459  }
460  ar.serialize("resetTime", reference);
461 }
463 
464 } // namespace openmsx
void setDouble(double value)
Definition: TclObject.cc:88
void execute(array_ref< TclObject > tokens, TclObject &result) const override
Show info on this topic.
Definition: MSXCPU.cc:313
void raiseNMI()
This method raises a non-maskable interrupt.
Definition: MSXCPU.cc:203
void setI(byte x)
Definition: CPURegs.hh:107
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
Definition: MSXCPU.cc:181
byte getC() const
Definition: CPURegs.hh:26
void setC(byte x)
Definition: CPURegs.hh:71
MSXCPUDebuggable(MSXMotherBoard &motherboard, MSXCPU &cpu)
Definition: MSXCPU.cc:346
byte getL2() const
Definition: CPURegs.hh:38
void setH2(byte x)
Definition: CPURegs.hh:82
void setR(byte x)
Definition: CPURegs.hh:108
void lowerIRQ()
This methods lowers the maskable interrupt again.
Definition: MSXCPU.cc:198
void setNextSyncPoint(EmuTime::param time)
Definition: MSXCPU.cc:175
TimeInfoTopic(InfoCommand &machineInfoCommand, MSXCPU &msxcpu)
Definition: MSXCPU.cc:284
byte getR() const
Definition: CPURegs.hh:63
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
Definition: MSXCPU.cc:163
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
Definition: MSXCPU.cc:214
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:27
unsigned getFreq() const
Definition: CPUClock.hh:14
void setB(byte x)
Definition: CPURegs.hh:70
CPURegs & getRegisters()
Definition: MSXCPU.cc:244
byte getSPl() const
Definition: CPURegs.hh:46
void setD2(byte x)
Definition: CPURegs.hh:80
void doReset(EmuTime::param time)
Reset CPU.
Definition: MSXCPU.cc:120
void setIM(byte x)
Definition: CPURegs.hh:106
void setF2(byte x)
Definition: CPURegs.hh:77
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: MSXCPU.cc:262
void setCPU(MSXCPU *cpu_)
Definition: Debugger.hh:35
void setPaused(bool paused)
(un)pause CPU.
Definition: MSXCPU.cc:270
void setE(byte x)
Definition: CPURegs.hh:73
bool getIFF1() const
Definition: CPURegs.hh:64
void setPCh(byte x)
Definition: CPURegs.hh:88
void setIFF1(bool x)
Definition: CPURegs.hh:109
byte getF2() const
Definition: CPURegs.hh:32
void setIYh(byte x)
Definition: CPURegs.hh:86
byte getC2() const
Definition: CPURegs.hh:34
byte getA2() const
Definition: CPURegs.hh:31
MSXCPU(MSXMotherBoard &motherboard)
Definition: MSXCPU.cc:59
void invalidateMemCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
Definition: MSXCPU.cc:187
byte getPCl() const
Definition: CPURegs.hh:44
byte getIYl() const
Definition: CPURegs.hh:42
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
Definition: MSXCPU.cc:139
void setA2(byte x)
Definition: CPURegs.hh:76
void setPCl(byte x)
Definition: CPURegs.hh:89
byte getIM() const
Definition: CPURegs.hh:61
void setIYl(byte x)
Definition: CPURegs.hh:87
void wait(EmuTime::param time)
Definition: MSXCPU.cc:225
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
CPUFreqInfoTopic(InfoCommand &machineInfoCommand, const string &name, CPUClock &clock)
Definition: MSXCPU.cc:306
void setCPU(MSXCPU *cpu_)
Definition: Scheduler.hh:46
byte getPCh() const
Definition: CPURegs.hh:43
byte read(unsigned address) override
Definition: MSXCPU.cc:352
void setSPl(byte x)
Definition: CPURegs.hh:91
void serialize(Archive &ar, unsigned version)
Definition: MSXCPU.cc:436
void setA(byte x)
Definition: CPURegs.hh:68
void setL(byte x)
Definition: CPURegs.hh:75
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:7
void setH(byte x)
Definition: CPURegs.hh:74
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:32
string help(const vector< string > &tokens) const override
Print help for this topic.
Definition: MSXCPU.cc:319
byte getIYh() const
Definition: CPURegs.hh:41
byte getH() const
Definition: CPURegs.hh:29
void setE2(byte x)
Definition: CPURegs.hh:81
byte getD() const
Definition: CPURegs.hh:27
void setB2(byte x)
Definition: CPURegs.hh:78
bool debugGetAfterEI() const
Definition: CPURegs.hh:140
void raiseIRQ()
This method raises a maskable interrupt.
Definition: MSXCPU.cc:193
void lowerNMI()
This methods lowers the non-maskable interrupt again.
Definition: MSXCPU.cc:208
byte getB2() const
Definition: CPURegs.hh:33
void setInterface(MSXCPUInterface *interf)
Definition: MSXCPU.cc:114
byte getL() const
Definition: CPURegs.hh:30
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void setL2(byte x)
Definition: CPURegs.hh:83
byte getD2() const
Definition: CPURegs.hh:35
byte getSPh() const
Definition: CPURegs.hh:45
void waitCycles(unsigned cycles)
Definition: MSXCPU.cc:231
void setIXl(byte x)
Definition: CPURegs.hh:85
void execute(array_ref< TclObject > tokens, TclObject &result) const override
Show info on this topic.
Definition: MSXCPU.cc:291
void setSPh(byte x)
Definition: CPURegs.hh:90
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
Definition: MSXCPU.cc:220
byte getIXh() const
Definition: CPURegs.hh:39
void setF(byte x)
Definition: CPURegs.hh:69
void setD(byte x)
Definition: CPURegs.hh:72
byte getF() const
Definition: CPURegs.hh:24
void setInt(int value)
Definition: TclObject.cc:66
byte getB() const
Definition: CPURegs.hh:25
void write(unsigned address, byte value) override
Definition: MSXCPU.cc:390
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
Definition: MSXCPU.cc:158
byte getA() const
Definition: CPURegs.hh:23
bool isR800Active() const
Is the R800 currently active?
Definition: MSXCPU.hh:97
byte getE2() const
Definition: CPURegs.hh:36
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
Definition: MSXCPU.cc:128
byte getH2() const
Definition: CPURegs.hh:37
size_t size(string_ref utf8)
void setIFF2(bool x)
Definition: CPURegs.hh:110
void setC2(byte x)
Definition: CPURegs.hh:79
byte getE() const
Definition: CPURegs.hh:28
void waitCyclesR800(unsigned cycles)
Definition: MSXCPU.cc:237
void setIXh(byte x)
Definition: CPURegs.hh:84
byte getIXl() const
Definition: CPURegs.hh:40
std::unique_ptr< T > make_unique()
Definition: memory.hh:27
byte getI() const
Definition: CPURegs.hh:62
bool getIFF2() const
Definition: CPURegs.hh:65
string help(const vector< string > &tokens) const override
Print help for this topic.
Definition: MSXCPU.cc:298
#define UNREACHABLE
Definition: unreachable.hh:35