openMSX
MSXCPU.cc
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1 #include "MSXCPU.hh"
2 #include "MSXMotherBoard.hh"
3 #include "Debugger.hh"
4 #include "Scheduler.hh"
5 #include "IntegerSetting.hh"
6 #include "CPUCore.hh"
7 #include "Z80.hh"
8 #include "R800.hh"
9 #include "TclObject.hh"
10 #include "serialize.hh"
11 #include "unreachable.hh"
12 #include "memory.hh"
13 #include <cassert>
14 
15 using std::string;
16 using std::vector;
17 
18 namespace openmsx {
19 
21  : motherboard(motherboard_)
22  , traceSetting(
23  motherboard.getCommandController(), "cputrace",
24  "CPU tracing on/off", false, Setting::DONT_SAVE)
25  , diHaltCallback(
26  motherboard.getCommandController(), "di_halt_callback",
27  "Tcl proc called when the CPU executed a DI/HALT sequence")
28  , z80(make_unique<CPUCore<Z80TYPE>>(
29  motherboard, "z80", traceSetting,
30  diHaltCallback, EmuTime::zero))
31  , r800(motherboard.isTurboR()
33  motherboard, "r800", traceSetting,
34  diHaltCallback, EmuTime::zero)
35  : nullptr)
36  , timeInfo(motherboard.getMachineInfoCommand(), *this)
37  , z80FreqInfo(motherboard.getMachineInfoCommand(), "z80_freq", *z80)
38  , r800FreqInfo(r800
39  ? make_unique<CPUFreqInfoTopic>(
40  motherboard.getMachineInfoCommand(), "r800_freq", *r800)
41  : nullptr)
42  , debuggable(motherboard_, *this)
43  , reference(EmuTime::zero)
44 {
45  z80Active = true; // setActiveCPU(CPU_Z80);
46  newZ80Active = z80Active;
47 
48  motherboard.getDebugger().setCPU(this);
49  motherboard.getScheduler().setCPU(this);
50  traceSetting.attach(*this);
51 
52  z80->freqLocked.attach(*this);
53  z80->freqValue.attach(*this);
54  if (r800) {
55  r800->freqLocked.attach(*this);
56  r800->freqValue.attach(*this);
57  }
58 }
59 
61 {
62  traceSetting.detach(*this);
63  z80->freqLocked.detach(*this);
64  z80->freqValue.detach(*this);
65  if (r800) {
66  r800->freqLocked.detach(*this);
67  r800->freqValue.detach(*this);
68  }
69  motherboard.getScheduler().setCPU(nullptr);
70  motherboard.getDebugger() .setCPU(nullptr);
71 }
72 
74 {
75  z80 ->setInterface(interface);
76  if (r800) r800->setInterface(interface);
77 }
78 
80 {
81  z80 ->doReset(time);
82  if (r800) r800->doReset(time);
83 
84  reference = time;
85 }
86 
88 {
89  if (cpu == CPU_R800) assert(r800);
90 
91  bool tmp = cpu == CPU_Z80;
92  if (tmp != z80Active) {
94  newZ80Active = tmp;
95  }
96 }
97 
98 void MSXCPU::setDRAMmode(bool dram)
99 {
100  assert(r800);
101  r800->setDRAMmode(dram);
102 }
103 
104 void MSXCPU::execute(bool fastForward)
105 {
106  if (z80Active != newZ80Active) {
107  EmuTime time = getCurrentTime();
108  z80Active = newZ80Active;
109  z80Active ? z80 ->warp(time)
110  : r800->warp(time);
111  invalidateMemCache(0x0000, 0x10000);
112  }
113  z80Active ? z80 ->execute(fastForward)
114  : r800->execute(fastForward);
115 }
116 
118 {
119  z80Active ? z80 ->exitCPULoopSync()
120  : r800->exitCPULoopSync();
121 }
123 {
124  z80Active ? z80 ->exitCPULoopAsync()
125  : r800->exitCPULoopAsync();
126 }
127 
128 EmuTime::param MSXCPU::getCurrentTime() const
129 {
130  return z80Active ? z80 ->getCurrentTime()
131  : r800->getCurrentTime();
132 }
133 
135 {
136  z80Active ? z80 ->setNextSyncPoint(time)
137  : r800->setNextSyncPoint(time);
138 }
139 
140 void MSXCPU::updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
141 {
142  invalidateMemCache(page * 0x4000, 0x4000);
143  if (r800) r800->updateVisiblePage(page, primarySlot, secondarySlot);
144 }
145 
146 void MSXCPU::invalidateMemCache(word start, unsigned size)
147 {
148  z80Active ? z80 ->invalidateMemCache(start, size)
149  : r800->invalidateMemCache(start, size);
150 }
151 
153 {
154  z80 ->raiseIRQ();
155  if (r800) r800->raiseIRQ();
156 }
158 {
159  z80 ->lowerIRQ();
160  if (r800) r800->lowerIRQ();
161 }
163 {
164  z80 ->raiseNMI();
165  if (r800) r800->raiseNMI();
166 }
168 {
169  z80 ->lowerNMI();
170  if (r800) r800->lowerNMI();
171 }
172 
173 bool MSXCPU::isM1Cycle(unsigned address) const
174 {
175  return z80Active ? z80 ->isM1Cycle(address)
176  : r800->isM1Cycle(address);
177 }
178 
179 void MSXCPU::setZ80Freq(unsigned freq)
180 {
181  z80->setFreq(freq);
182 }
183 
185 {
186  z80Active ? z80 ->wait(time)
187  : r800->wait(time);
188 }
189 
190 void MSXCPU::waitCycles(unsigned cycles)
191 {
192  z80Active ? z80 ->waitCycles(cycles)
193  : r800->waitCycles(cycles);
194 }
195 
196 void MSXCPU::waitCyclesR800(unsigned cycles)
197 {
198  if (isR800Active()) {
199  r800->waitCycles(cycles);
200  }
201 }
202 
204 {
205  if (z80Active) {
206  return *z80;
207  } else {
208  return *r800;
209  }
210 }
211 
212 void MSXCPU::update(const Setting& setting)
213 {
214  z80 ->update(setting);
215  if (r800) r800->update(setting);
216  exitCPULoopSync();
217 }
218 
219 // Command
220 
222  Interpreter& interp, array_ref<TclObject> tokens,
223  TclObject& result) const
224 {
225  z80Active ? z80 ->disasmCommand(interp, tokens, result)
226  : r800->disasmCommand(interp, tokens, result);
227 }
228 
229 void MSXCPU::setPaused(bool paused)
230 {
231  if (z80Active) {
232  z80 ->setExtHALT(paused);
233  z80 ->exitCPULoopSync();
234  } else {
235  r800->setExtHALT(paused);
236  r800->exitCPULoopSync();
237  }
238 }
239 
240 
241 // class TimeInfoTopic
242 
243 MSXCPU::TimeInfoTopic::TimeInfoTopic(
244  InfoCommand& machineInfoCommand, MSXCPU& msxcpu_)
245  : InfoTopic(machineInfoCommand, "time")
246  , msxcpu(msxcpu_)
247 {
248 }
249 
250 void MSXCPU::TimeInfoTopic::execute(
251  array_ref<TclObject> /*tokens*/, TclObject& result) const
252 {
253  EmuDuration dur = msxcpu.getCurrentTime() - msxcpu.reference;
254  result.setDouble(dur.toDouble());
255 }
256 
257 string MSXCPU::TimeInfoTopic::help(const vector<string>& /*tokens*/) const
258 {
259  return "Prints the time in seconds that the MSX is powered on\n";
260 }
261 
262 
263 // class CPUFreqInfoTopic
264 
265 MSXCPU::CPUFreqInfoTopic::CPUFreqInfoTopic(
266  InfoCommand& machineInfoCommand,
267  const string& name, CPUClock& clock_)
268  : InfoTopic(machineInfoCommand, name)
269  , clock(clock_)
270 {
271 }
272 
273 void MSXCPU::CPUFreqInfoTopic::execute(
274  array_ref<TclObject> /*tokens*/, TclObject& result) const
275 {
276  result.setInt(clock.getFreq());
277 }
278 
279 string MSXCPU::CPUFreqInfoTopic::help(const vector<string>& /*tokens*/) const
280 {
281  return "Returns the actual frequency of this CPU.\n"
282  "This frequency can vary because:\n"
283  " - the user has overridden the freq via the '{z80,r800}_freq' setting\n"
284  " - (only on some MSX machines) the MSX software can switch the Z80 between 2 frequencies\n"
285  "See also the '{z80,r800}_freq_locked' setting.\n";
286 }
287 
288 
289 // class Debuggable
290 
291 static const char* const CPU_REGS_DESC =
292  "Registers of the active CPU (Z80 or R800).\n"
293  "Each byte in this debuggable represents one 8 bit register:\n"
294  " 0 -> A 1 -> F 2 -> B 3 -> C\n"
295  " 4 -> D 5 -> E 6 -> H 7 -> L\n"
296  " 8 -> A' 9 -> F' 10 -> B' 11 -> C'\n"
297  " 12 -> D' 13 -> E' 14 -> H' 15 -> L'\n"
298  " 16 -> IXH 17 -> IXL 18 -> IYH 19 -> IYL\n"
299  " 20 -> PCH 21 -> PCL 22 -> SPH 23 -> SPL\n"
300  " 24 -> I 25 -> R 26 -> IM 27 -> IFF1/2\n"
301  "The last position (27) contains the IFF1 and IFF2 flags in respectively\n"
302  "bit 0 and 1. Bit 2 contains 'IFF1 AND last-instruction-was-not-EI', so\n"
303  "this effectively indicates that the CPU could accept an interrupt at\n"
304  "the start of the current instruction.\n";
305 
306 MSXCPU::Debuggable::Debuggable(MSXMotherBoard& motherboard, MSXCPU& cpu_)
307  : SimpleDebuggable(motherboard, "CPU regs", CPU_REGS_DESC, 28)
308  , cpu(cpu_)
309 {
310 }
311 
312 byte MSXCPU::Debuggable::read(unsigned address)
313 {
314  const CPURegs& regs = cpu.getRegisters();
315  switch (address) {
316  case 0: return regs.getA();
317  case 1: return regs.getF();
318  case 2: return regs.getB();
319  case 3: return regs.getC();
320  case 4: return regs.getD();
321  case 5: return regs.getE();
322  case 6: return regs.getH();
323  case 7: return regs.getL();
324  case 8: return regs.getA2();
325  case 9: return regs.getF2();
326  case 10: return regs.getB2();
327  case 11: return regs.getC2();
328  case 12: return regs.getD2();
329  case 13: return regs.getE2();
330  case 14: return regs.getH2();
331  case 15: return regs.getL2();
332  case 16: return regs.getIXh();
333  case 17: return regs.getIXl();
334  case 18: return regs.getIYh();
335  case 19: return regs.getIYl();
336  case 20: return regs.getPCh();
337  case 21: return regs.getPCl();
338  case 22: return regs.getSPh();
339  case 23: return regs.getSPl();
340  case 24: return regs.getI();
341  case 25: return regs.getR();
342  case 26: return regs.getIM();
343  case 27: return 1 * regs.getIFF1() +
344  2 * regs.getIFF2() +
345  4 * (regs.getIFF1() && !regs.debugGetAfterEI());
346  default: UNREACHABLE; return 0;
347  }
348 }
349 
350 void MSXCPU::Debuggable::write(unsigned address, byte value)
351 {
352  CPURegs& regs = cpu.getRegisters();
353  switch (address) {
354  case 0: regs.setA(value); break;
355  case 1: regs.setF(value); break;
356  case 2: regs.setB(value); break;
357  case 3: regs.setC(value); break;
358  case 4: regs.setD(value); break;
359  case 5: regs.setE(value); break;
360  case 6: regs.setH(value); break;
361  case 7: regs.setL(value); break;
362  case 8: regs.setA2(value); break;
363  case 9: regs.setF2(value); break;
364  case 10: regs.setB2(value); break;
365  case 11: regs.setC2(value); break;
366  case 12: regs.setD2(value); break;
367  case 13: regs.setE2(value); break;
368  case 14: regs.setH2(value); break;
369  case 15: regs.setL2(value); break;
370  case 16: regs.setIXh(value); break;
371  case 17: regs.setIXl(value); break;
372  case 18: regs.setIYh(value); break;
373  case 19: regs.setIYl(value); break;
374  case 20: regs.setPCh(value); break;
375  case 21: regs.setPCl(value); break;
376  case 22: regs.setSPh(value); break;
377  case 23: regs.setSPl(value); break;
378  case 24: regs.setI(value); break;
379  case 25: regs.setR(value); break;
380  case 26:
381  if (value < 3) regs.setIM(value);
382  break;
383  case 27:
384  regs.setIFF1((value & 0x01) != 0);
385  regs.setIFF2((value & 0x02) != 0);
386  // can't change afterEI
387  break;
388  default:
389  UNREACHABLE;
390  }
391 }
392 
393 // version 1: initial version
394 // version 2: activeCPU,newCPU -> z80Active,newZ80Active
395 template<typename Archive>
396 void MSXCPU::serialize(Archive& ar, unsigned version)
397 {
398  if (ar.versionAtLeast(version, 2)) {
399  ar.serialize("z80", *z80);
400  if (r800) ar.serialize("r800", *r800);
401  ar.serialize("z80Active", z80Active);
402  ar.serialize("newZ80Active", newZ80Active);
403  } else {
404  // backwards-compatibility
405  assert(ar.isLoader());
406 
407  ar.serializeWithID("z80", *z80);
408  if (r800) ar.serializeWithID("r800", *r800);
409  CPUBase* activeCPU = nullptr;
410  CPUBase* newCPU = nullptr;
411  ar.serializePointerID("activeCPU", activeCPU);
412  ar.serializePointerID("newCPU", newCPU);
413  z80Active = activeCPU == z80.get();
414  if (newCPU) {
415  newZ80Active = newCPU == z80.get();
416  } else {
417  newZ80Active = z80Active;
418  }
419  }
420  ar.serialize("resetTime", reference);
421 }
423 
424 } // namespace openmsx
void raiseNMI()
This method raises a non-maskable interrupt.
Definition: MSXCPU.cc:162
void updateVisiblePage(byte page, byte primarySlot, byte secondarySlot)
Inform CPU of bank switch.
Definition: MSXCPU.cc:140
void lowerIRQ()
This methods lowers the maskable interrupt again.
Definition: MSXCPU.cc:157
void setNextSyncPoint(EmuTime::param time)
Definition: MSXCPU.cc:134
void exitCPULoopAsync()
See CPUCore::exitCPULoopAsync()
Definition: MSXCPU.cc:122
bool isM1Cycle(unsigned address) const
Should only be used from within a MSXDevice::readMem() method.
Definition: MSXCPU.cc:173
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:27
CPURegs & getRegisters()
Definition: MSXCPU.cc:203
void doReset(EmuTime::param time)
Reset CPU.
Definition: MSXCPU.cc:79
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: MSXCPU.cc:221
void setCPU(MSXCPU *cpu_)
Definition: Debugger.hh:35
void setPaused(bool paused)
(un)pause CPU.
Definition: MSXCPU.cc:229
MSXCPU(MSXMotherBoard &motherboard)
Definition: MSXCPU.cc:20
void invalidateMemCache(word start, unsigned size)
Invalidate the CPU its cache for the interval [start, start + size) For example MSXMemoryMapper and M...
Definition: MSXCPU.cc:146
void setDRAMmode(bool dram)
Sets DRAM or ROM mode (influences memory access speed for R800).
Definition: MSXCPU.cc:98
void attach(Observer< T > &observer)
Definition: Subject.hh:52
void wait(EmuTime::param time)
Definition: MSXCPU.cc:184
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
void setCPU(MSXCPU *cpu_)
Definition: Scheduler.hh:43
void serialize(Archive &ar, unsigned version)
Definition: MSXCPU.cc:396
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:32
void raiseIRQ()
This method raises a maskable interrupt.
Definition: MSXCPU.cc:152
void lowerNMI()
This methods lowers the non-maskable interrupt again.
Definition: MSXCPU.cc:167
void setInterface(MSXCPUInterface *interf)
Definition: MSXCPU.cc:73
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void waitCycles(unsigned cycles)
Definition: MSXCPU.cc:190
void setZ80Freq(unsigned freq)
Switch the Z80 clock freq.
Definition: MSXCPU.cc:179
void detach(Observer< T > &observer)
Definition: Subject.hh:58
void exitCPULoopSync()
See CPUCore::exitCPULoopsync()
Definition: MSXCPU.cc:117
bool isR800Active() const
Is the R800 currently active?
Definition: MSXCPU.hh:96
void setActiveCPU(CPUType cpu)
Switch between Z80/R800.
Definition: MSXCPU.cc:87
size_t size(string_ref utf8)
void waitCyclesR800(unsigned cycles)
Definition: MSXCPU.cc:196
std::unique_ptr< T > make_unique()
Definition: memory.hh:27
#define UNREACHABLE
Definition: unreachable.hh:35