openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "BooleanSetting.hh"
167 #include "IntegerSetting.hh"
168 #include "TclCallback.hh"
169 #include "Dasm.hh"
170 #include "Z80.hh"
171 #include "R800.hh"
172 #include "Thread.hh"
173 #include "endian.hh"
174 #include "likely.hh"
175 #include "inline.hh"
176 #include "unreachable.hh"
177 #include "memory.hh"
178 #include <iomanip>
179 #include <iostream>
180 #include <type_traits>
181 #include <cassert>
182 #include <cstring>
183 
184 
185 //
186 // #define USE_COMPUTED_GOTO
187 //
188 // Computed goto's are not enabled by default:
189 // - Computed goto's are a gcc extension, it's not part of the official c++
190 // standard. So this will only work if you use gcc as your compiler (it
191 // won't work with visual c++ for example)
192 // - This is only beneficial on CPUs with branch prediction for indirect jumps
193 // and a reasonable amout of cache. For example it is very benefical for a
194 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
195 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
196 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
197 // But even on more recent gcc versions it still requires around 700MB.
198 //
199 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
200 // flag to the compiler. This is for example done in the super-opt flavour.
201 // See build/flavour-super-opt.mk
202 
203 
204 using std::string;
205 
206 namespace openmsx {
207 
208 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
209 // As a quick hack I put these two lines here because I found it overkill to
210 // create two files each containing only a single line.
211 // Technically these two lines _are_ required according to the c++ standard.
212 // Though usually it works just find without them, but during experiments I did
213 // get a link error when these lines were missing (it only happened during a
214 // debug build with some specific compiler version and only with some
215 // combination of other code changes, but again when strictly following the
216 // language rules, these lines should be here).
217 // ... But visual studio is not fully standard compliant, see also comment
218 // in SectorAccesibleDisk.cc
219 #ifndef _MSC_VER
220 const int Z80TYPE ::CLOCK_FREQ;
221 const int R800TYPE::CLOCK_FREQ;
222 #endif
223 
224 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
225 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
226 
227 // flag positions
228 static const byte S_FLAG = 0x80;
229 static const byte Z_FLAG = 0x40;
230 static const byte Y_FLAG = 0x20;
231 static const byte H_FLAG = 0x10;
232 static const byte X_FLAG = 0x08;
233 static const byte V_FLAG = 0x04;
234 static const byte P_FLAG = V_FLAG;
235 static const byte N_FLAG = 0x02;
236 static const byte C_FLAG = 0x01;
237 
238 // flag-register tables, initialized at run-time
239 static byte ZSTable[256];
240 static byte ZSXYTable[256];
241 static byte ZSPTable[256];
242 static byte ZSPXYTable[256];
243 static byte ZSPHTable[256];
244 
245 static const byte ZS0 = Z_FLAG;
246 static const byte ZSXY0 = Z_FLAG;
247 static const byte ZSP0 = Z_FLAG | V_FLAG;
248 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
249 static const byte ZS255 = S_FLAG;
250 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
251 
252 typedef signed char offset;
253 
254 // Global variable, because it should be shared between Z80 and R800.
255 // It must not be shared between the CPUs of different MSX machines, but
256 // the (logical) lifetime of this variable cannot overlap between execution
257 // of two MSX machines.
258 static word start_pc;
259 
260 // conditions
261 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
262 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
263 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
264 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
265 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
266 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
267 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
268 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
269 struct CondTrue { bool operator()(byte) const { return true; } };
270 
271 static void initTables()
272 {
273  static bool alreadyInit = false;
274  if (alreadyInit) return;
275  alreadyInit = true;
276 
277  for (int i = 0; i < 256; ++i) {
278  byte zFlag = (i == 0) ? Z_FLAG : 0;
279  byte sFlag = i & S_FLAG;
280  byte xFlag = i & X_FLAG;
281  byte yFlag = i & Y_FLAG;
282  byte vFlag = V_FLAG;
283  for (int v = 128; v != 0; v >>= 1) {
284  if (i & v) vFlag ^= V_FLAG;
285  }
286  ZSTable [i] = zFlag | sFlag;
287  ZSXYTable [i] = zFlag | sFlag | xFlag | yFlag;
288  ZSPTable [i] = zFlag | sFlag | vFlag;
289  ZSPXYTable[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
290  ZSPHTable [i] = zFlag | sFlag | vFlag | H_FLAG;
291  }
292  assert(ZSTable [ 0] == ZS0);
293  assert(ZSXYTable [ 0] == ZSXY0);
294  assert(ZSPTable [ 0] == ZSP0);
295  assert(ZSPXYTable[ 0] == ZSPXY0);
296  assert(ZSTable [255] == ZS255);
297  assert(ZSXYTable [255] == ZSXY255);
298 }
299 
300 template<class T> CPUCore<T>::CPUCore(
301  MSXMotherBoard& motherboard_, const string& name,
302  const BooleanSetting& traceSetting_,
303  TclCallback& diHaltCallback_, EmuTime::param time)
304  : CPURegs(T::isR800())
305  , T(time, motherboard_.getScheduler())
306  , motherboard(motherboard_)
307  , scheduler(motherboard.getScheduler())
308  , interface(nullptr)
309  , traceSetting(traceSetting_)
310  , diHaltCallback(diHaltCallback_)
311  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
312  "Non-zero if there are pending IRQs (thus CPU would enter "
313  "interrupt routine in EI mode).",
314  0)
315  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
316  "This probe is only useful to set a breakpoint on (the value "
317  "return by read is meaningless). The breakpoint gets triggered "
318  "right after the CPU accepted an IRQ.")
319  , freqLocked(make_unique<BooleanSetting>(
320  motherboard.getCommandController(), name + "_freq_locked",
321  "real (locked) or custom (unlocked) " + name + " frequency",
322  true))
323  , freqValue(make_unique<IntegerSetting>(
324  motherboard.getCommandController(), name + "_freq",
325  "custom " + name + " frequency (only valid when unlocked)",
326  T::CLOCK_FREQ, 1000000, 1000000000))
327  , freq(T::CLOCK_FREQ)
328  , NMIStatus(0)
329  , nmiEdge(false)
330  , exitLoop(false)
331  , tracingEnabled(traceSetting.getBoolean())
332  , isTurboR(motherboard.isTurboR())
333 {
334  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
335  "keep CPUCore non-virtual to keep PC at offset 0");
336  doSetFreq();
337  doReset(time);
338 
339  initTables();
340 }
341 
342 template<class T> void CPUCore<T>::warp(EmuTime::param time)
343 {
344  assert(T::getTimeFast() <= time);
345  T::setTime(time);
346 }
347 
349 {
350  return T::getTime();
351 }
352 
353 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
354 {
355  unsigned first = start / CacheLine::SIZE;
356  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
357  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
358  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
359  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
360  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
361 }
362 
363 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
364 {
365  // AF and SP are 0xFFFF
366  // PC, R, IFF1, IFF2, HALT and IM are 0x0
367  // all others are random
368  setAF(0xFFFF);
369  setBC(0xFFFF);
370  setDE(0xFFFF);
371  setHL(0xFFFF);
372  setIX(0xFFFF);
373  setIY(0xFFFF);
374  setPC(0x0000);
375  setSP(0xFFFF);
376  setAF2(0xFFFF);
377  setBC2(0xFFFF);
378  setDE2(0xFFFF);
379  setHL2(0xFFFF);
380  clearNextAfter();
381  copyNextAfter();
382  setIFF1(false);
383  setIFF2(false);
384  setHALT(false);
385  setExtHALT(false);
386  setIM(0);
387  setI(0x00);
388  setR(0x00);
389  T::setMemPtr(0xFFFF);
390  invalidateMemCache(0x0000, 0x10000);
391 
392  // We expect this assert to be valid
393  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
394  // But it's disabled for the following reason:
395  // 'motion' (IRC nickname) managed to create a replay file that
396  // contains a reset command that falls in the middle of a Z80
397  // instruction. Replayed commands go via the Scheduler, and are
398  // (typically) executed right after a complete CPU instruction. So
399  // the CPU is (slightly) ahead in time of the about to be executed
400  // reset command.
401  // Normally this situation should never occur: console commands,
402  // hotkeys, commands over clicomm, ... are all handled via the global
403  // event mechanism. Such global events are scheduled between CPU
404  // instructions, so also in a replay they should fall between CPU
405  // instructions.
406  // However if for some reason the timing of the emulation changed
407  // (improved emulation accuracy or a bug so that emulation isn't
408  // deterministic or the replay file was edited, ...), then the above
409  // reasoning no longer holds and the assert can trigger.
410  // We need to be robust against loading older replays (when emulation
411  // timing has changed). So in that respect disabling the assert is
412  // good. Though in the example above (motion's replay) it's not clear
413  // whether the assert is really triggered by mixing an old replay
414  // with a newer openMSX version. In any case so far we haven't been
415  // able to reproduce this assert by recording and replaying using a
416  // single openMSX version.
417  T::setTime(time);
418 
419  assert(NMIStatus == 0); // other devices must reset their NMI source
420  assert(IRQStatus == 0); // other devices must reset their IRQ source
421 }
422 
423 // I believe the following two methods are thread safe even without any
424 // locking. The worst that can happen is that we occasionally needlessly
425 // exit the CPU loop, but that's harmless
426 // TODO thread issues are always tricky, can someone confirm this really
427 // is thread safe
428 template<class T> void CPUCore<T>::exitCPULoopAsync()
429 {
430  // can get called from non-main threads
431  exitLoop = true;
432 }
433 template<class T> void CPUCore<T>::exitCPULoopSync()
434 {
435  assert(Thread::isMainThread());
436  exitLoop = true;
437  T::disableLimit();
438 }
439 template<class T> inline bool CPUCore<T>::needExitCPULoop()
440 {
441  // always executed in main thread
442  if (unlikely(exitLoop)) {
443  exitLoop = false;
444  return true;
445  }
446  return false;
447 }
448 
449 template<class T> void CPUCore<T>::setSlowInstructions()
450 {
451  slowInstructions = 2;
452  T::disableLimit();
453 }
454 
455 template<class T> void CPUCore<T>::raiseIRQ()
456 {
457  assert(IRQStatus >= 0);
458  if (IRQStatus == 0) {
459  setSlowInstructions();
460  }
461  IRQStatus = IRQStatus + 1;
462 }
463 
464 template<class T> void CPUCore<T>::lowerIRQ()
465 {
466  IRQStatus = IRQStatus - 1;
467  assert(IRQStatus >= 0);
468 }
469 
470 template<class T> void CPUCore<T>::raiseNMI()
471 {
472  // NMIs are currently disabled, they are anyway not used in MSX and
473  // not having to check for them allows to emulate slightly faster
474  UNREACHABLE;
475  assert(NMIStatus >= 0);
476  if (NMIStatus == 0) {
477  nmiEdge = true;
478  setSlowInstructions();
479  }
480  NMIStatus++;
481 }
482 
483 template<class T> void CPUCore<T>::lowerNMI()
484 {
485  NMIStatus--;
486  assert(NMIStatus >= 0);
487 }
488 
489 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
490 {
491  // PC was already increased, so decrease again
492  return address == ((getPC() - 1) & 0xFFFF);
493 }
494 
495 template<class T> void CPUCore<T>::wait(EmuTime::param time)
496 {
497  assert(time >= getCurrentTime());
498  scheduler.schedule(time);
499  T::advanceTime(time);
500 }
501 
502 template<class T> void CPUCore<T>::waitCycles(unsigned cycles)
503 {
504  T::add(cycles);
505 }
506 
507 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
508 {
509  T::setLimit(time);
510 }
511 
512 
513 static inline char toHex(byte x)
514 {
515  return (x < 10) ? (x + '0') : (x - 10 + 'A');
516 }
517 static void toHex(byte x, char* buf)
518 {
519  buf[0] = toHex(x / 16);
520  buf[1] = toHex(x & 15);
521 }
522 
523 template<class T> void CPUCore<T>::disasmCommand(
524  Interpreter& interp, array_ref<TclObject> tokens, TclObject& result) const
525 {
526  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
527  byte outBuf[4];
528  std::string dasmOutput;
529  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
530  T::getTimeFast());
531  result.addListElement(dasmOutput);
532  char tmp[3]; tmp[2] = 0;
533  for (unsigned i = 0; i < len; ++i) {
534  toHex(outBuf[i], tmp);
535  result.addListElement(tmp);
536  }
537 }
538 
539 template<class T> void CPUCore<T>::update(const Setting& setting)
540 {
541  if (&setting == freqLocked.get()) {
542  doSetFreq();
543  } else if (&setting == freqValue.get()) {
544  doSetFreq();
545  } else if (&setting == &traceSetting) {
546  tracingEnabled = traceSetting.getBoolean();
547  }
548 }
549 
550 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
551 {
552  freq = freq_;
553  doSetFreq();
554 }
555 
556 template<class T> void CPUCore<T>::doSetFreq()
557 {
558  if (freqLocked->getBoolean()) {
559  // locked, use value set via setFreq()
560  T::setFreq(freq);
561  } else {
562  // unlocked, use value set by user
563  T::setFreq(freqValue->getInt());
564  }
565 }
566 
567 
568 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
569 {
570  EmuTime time = T::getTimeFast(cc);
571  scheduler.schedule(time);
572  byte result = interface->readIO(port, time);
573  // note: no forced page-break after IO
574  return result;
575 }
576 
577 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
578 {
579  EmuTime time = T::getTimeFast(cc);
580  scheduler.schedule(time);
581  interface->writeIO(port, value, time);
582  // note: no forced page-break after IO
583 }
584 
585 template<class T> template<bool PRE_PB, bool POST_PB>
586 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
587 {
588  // not cached
589  unsigned high = address >> CacheLine::BITS;
590  if (!readCacheTried[high]) {
591  // try to cache now
592  unsigned addrBase = address & CacheLine::HIGH;
593  if (const byte* line = interface->getReadCacheLine(addrBase)) {
594  // cached ok
595  T::template PRE_MEM<PRE_PB, POST_PB>(address);
596  T::template POST_MEM< POST_PB>(address);
597  readCacheLine[high] = line - addrBase;
598  return readCacheLine[high][address];
599  }
600  }
601  // uncacheable
602  readCacheTried[high] = true;
603  T::template PRE_MEM<PRE_PB, POST_PB>(address);
604  EmuTime time = T::getTimeFast(cc);
605  scheduler.schedule(time);
606  byte result = interface->readMem(address, time);
607  T::template POST_MEM<POST_PB>(address);
608  return result;
609 }
610 template<class T> template<bool PRE_PB, bool POST_PB>
611 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
612 {
613  const byte* line = readCacheLine[address >> CacheLine::BITS];
614  if (likely(line != nullptr)) {
615  // cached, fast path
616  T::template PRE_MEM<PRE_PB, POST_PB>(address);
617  T::template POST_MEM< POST_PB>(address);
618  return line[address];
619  } else {
620  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
621  }
622 }
623 template<class T> template<bool PRE_PB, bool POST_PB>
624 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
625 {
626  static const bool PRE = T::template Normalize<PRE_PB >::value;
627  static const bool POST = T::template Normalize<POST_PB>::value;
628  return RDMEM_impl2<PRE, POST>(address, cc);
629 }
630 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
631 {
632  unsigned address = getPC();
633  setPC(address + 1);
634  return RDMEM_impl<false, false>(address, cc);
635 }
636 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
637 {
638  return RDMEM_impl<true, true>(address, cc);
639 }
640 
641 template<class T> template<bool PRE_PB, bool POST_PB>
642 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
643 {
644  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
645  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
646  return res;
647 }
648 template<class T> template<bool PRE_PB, bool POST_PB>
649 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
650 {
651  const byte* line = readCacheLine[address >> CacheLine::BITS];
652  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
653  // fast path: cached and two bytes in same cache line
654  T::template PRE_WORD<PRE_PB, POST_PB>(address);
655  T::template POST_WORD< POST_PB>(address);
656  return Endian::read_UA_L16(&line[address]);
657  } else {
658  // slow path, not inline
659  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
660  }
661 }
662 template<class T> template<bool PRE_PB, bool POST_PB>
663 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
664 {
665  static const bool PRE = T::template Normalize<PRE_PB >::value;
666  static const bool POST = T::template Normalize<POST_PB>::value;
667  return RD_WORD_impl2<PRE, POST>(address, cc);
668 }
669 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
670 {
671  unsigned addr = getPC();
672  setPC(addr + 2);
673  return RD_WORD_impl<false, false>(addr, cc);
674 }
675 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
676  unsigned address, unsigned cc)
677 {
678  return RD_WORD_impl<true, true>(address, cc);
679 }
680 
681 template<class T> template<bool PRE_PB, bool POST_PB>
682 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
683 {
684  // not cached
685  unsigned high = address >> CacheLine::BITS;
686  if (!writeCacheTried[high]) {
687  // try to cache now
688  unsigned addrBase = address & CacheLine::HIGH;
689  if (byte* line = interface->getWriteCacheLine(addrBase)) {
690  // cached ok
691  T::template PRE_MEM<PRE_PB, POST_PB>(address);
692  T::template POST_MEM< POST_PB>(address);
693  writeCacheLine[high] = line - addrBase;
694  writeCacheLine[high][address] = value;
695  return;
696  }
697  }
698  // uncacheable
699  writeCacheTried[high] = true;
700  T::template PRE_MEM<PRE_PB, POST_PB>(address);
701  EmuTime time = T::getTimeFast(cc);
702  scheduler.schedule(time);
703  interface->writeMem(address, value, time);
704  T::template POST_MEM<POST_PB>(address);
705 }
706 template<class T> template<bool PRE_PB, bool POST_PB>
708  unsigned address, byte value, unsigned cc)
709 {
710  byte* line = writeCacheLine[address >> CacheLine::BITS];
711  if (likely(line != nullptr)) {
712  // cached, fast path
713  T::template PRE_MEM<PRE_PB, POST_PB>(address);
714  T::template POST_MEM< POST_PB>(address);
715  line[address] = value;
716  } else {
717  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
718  }
719 }
720 template<class T> template<bool PRE_PB, bool POST_PB>
722  unsigned address, byte value, unsigned cc)
723 {
724  static const bool PRE = T::template Normalize<PRE_PB >::value;
725  static const bool POST = T::template Normalize<POST_PB>::value;
726  WRMEM_impl2<PRE, POST>(address, value, cc);
727 }
728 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
729  unsigned address, byte value, unsigned cc)
730 {
731  WRMEM_impl<true, true>(address, value, cc);
732 }
733 
734 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
735  unsigned address, unsigned value, unsigned cc)
736 {
737  WRMEM_impl<true, false>( address, value & 255, cc);
738  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
739 }
740 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
741  unsigned address, unsigned value, unsigned cc)
742 {
743  byte* line = writeCacheLine[address >> CacheLine::BITS];
744  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
745  // fast path: cached and two bytes in same cache line
746  T::template PRE_WORD<true, true>(address);
747  T::template POST_WORD< true>(address);
748  Endian::write_UA_L16(&line[address], value);
749  } else {
750  // slow path, not inline
751  WR_WORD_slow(address, value, cc);
752  }
753 }
754 
755 // same as WR_WORD, but writes high byte first
756 template<class T> template<bool PRE_PB, bool POST_PB>
758  unsigned address, unsigned value, unsigned cc)
759 {
760  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
761  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
762 }
763 template<class T> template<bool PRE_PB, bool POST_PB>
765  unsigned address, unsigned value, unsigned cc)
766 {
767  byte* line = writeCacheLine[address >> CacheLine::BITS];
768  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
769  // fast path: cached and two bytes in same cache line
770  T::template PRE_WORD<PRE_PB, POST_PB>(address);
771  T::template POST_WORD< POST_PB>(address);
772  Endian::write_UA_L16(&line[address], value);
773  } else {
774  // slow path, not inline
775  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
776  }
777 }
778 template<class T> template<bool PRE_PB, bool POST_PB>
780  unsigned address, unsigned value, unsigned cc)
781 {
782  static const bool PRE = T::template Normalize<PRE_PB >::value;
783  static const bool POST = T::template Normalize<POST_PB>::value;
784  WR_WORD_rev2<PRE, POST>(address, value, cc);
785 }
786 
787 
788 // NMI interrupt
789 template<class T> inline void CPUCore<T>::nmi()
790 {
791  incR(1);
792  setHALT(false);
793  setIFF1(false);
794  PUSH<T::EE_NMI_1>(getPC());
795  setPC(0x0066);
796  T::add(T::CC_NMI);
797 }
798 
799 // IM0 interrupt
800 template<class T> inline void CPUCore<T>::irq0()
801 {
802  // TODO current implementation only works for 1-byte instructions
803  // ok for MSX
804  assert(interface->readIRQVector() == 0xFF);
805  incR(1);
806  setHALT(false);
807  setIFF1(false);
808  setIFF2(false);
809  PUSH<T::EE_IRQ0_1>(getPC());
810  setPC(0x0038);
811  T::setMemPtr(getPC());
812  T::add(T::CC_IRQ0);
813 }
814 
815 // IM1 interrupt
816 template<class T> inline void CPUCore<T>::irq1()
817 {
818  incR(1);
819  setHALT(false);
820  setIFF1(false);
821  setIFF2(false);
822  PUSH<T::EE_IRQ1_1>(getPC());
823  setPC(0x0038);
824  T::setMemPtr(getPC());
825  T::add(T::CC_IRQ1);
826 }
827 
828 // IM2 interrupt
829 template<class T> inline void CPUCore<T>::irq2()
830 {
831  incR(1);
832  setHALT(false);
833  setIFF1(false);
834  setIFF2(false);
835  PUSH<T::EE_IRQ2_1>(getPC());
836  unsigned x = interface->readIRQVector() | (getI() << 8);
837  setPC(RD_WORD(x, T::CC_IRQ2_2));
838  T::setMemPtr(getPC());
839  T::add(T::CC_IRQ2);
840 }
841 
842 template<class T>
843 void CPUCore<T>::executeInstructions()
844 {
845  assert(isNextAfterClear());
846 
847 #ifdef USE_COMPUTED_GOTO
848  // Addresses of all main-opcode routines,
849  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
850  static void* opcodeTable[256] = {
851  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
852  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
853  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
854  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
855  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
856  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
857  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
858  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
859  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
860  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
861  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
862  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
863  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
864  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
865  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
866  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
867  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
868  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
869  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
870  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
871  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
872  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
873  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
874  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
875  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
876  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
877  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
878  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
879  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
880  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
881  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
882  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
883  };
884 
885 // Check T::limitReached(). If it's OK to continue,
886 // fetch and execute next instruction.
887 #define NEXT \
888  T::add(c); \
889  T::R800Refresh(*this); \
890  if (likely(!T::limitReached())) { \
891  incR(1); \
892  unsigned address = getPC(); \
893  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
894  if (likely(line != nullptr)) { \
895  setPC(address + 1); \
896  T::template PRE_MEM<false, false>(address); \
897  T::template POST_MEM< false>(address); \
898  byte op = line[address]; \
899  goto *(opcodeTable[op]); \
900  } else { \
901  goto fetchSlow; \
902  } \
903  } \
904  return;
905 
906 // After some instructions we must always exit the CPU loop (ei, halt, retn)
907 #define NEXT_STOP \
908  T::add(c); \
909  T::R800Refresh(*this); \
910  assert(T::limitReached()); \
911  return;
912 
913 #define NEXT_EI \
914  T::add(c); \
915  /* !! NO T::R800Refresh(*this); !! */ \
916  assert(T::limitReached()); \
917  return;
918 
919 // Define a label (instead of case in a switch statement)
920 #define CASE(X) op##X:
921 
922 #else // USE_COMPUTED_GOTO
923 
924 #define NEXT \
925  T::add(c); \
926  T::R800Refresh(*this); \
927  if (likely(!T::limitReached())) { \
928  goto start; \
929  } \
930  return;
931 
932 #define NEXT_STOP \
933  T::add(c); \
934  T::R800Refresh(*this); \
935  assert(T::limitReached()); \
936  return;
937 
938 #define NEXT_EI \
939  T::add(c); \
940  /* !! NO T::R800Refresh(*this); !! */ \
941  assert(T::limitReached()); \
942  return;
943 
944 #define CASE(X) case 0x##X:
945 
946 #endif // USE_COMPUTED_GOTO
947 
948 #ifndef USE_COMPUTED_GOTO
949 start:
950 #endif
951  unsigned ixy; // for dd_cb/fd_cb
952  byte opcodeMain = RDMEM_OPCODE(T::CC_MAIN);
953  incR(1);
954 #ifdef USE_COMPUTED_GOTO
955  goto *(opcodeTable[opcodeMain]);
956 
957 fetchSlow: {
958  unsigned address = getPC();
959  setPC(address + 1);
960  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
961  goto *(opcodeTable[opcodeSlow]);
962 }
963 #endif
964 
965 #ifndef USE_COMPUTED_GOTO
966 switchopcode:
967  switch (opcodeMain) {
968 CASE(40) // ld b,b
969 CASE(49) // ld c,c
970 CASE(52) // ld d,d
971 CASE(5B) // ld e,e
972 CASE(64) // ld h,h
973 CASE(6D) // ld l,l
974 CASE(7F) // ld a,a
975 #endif
976 CASE(00) { int c = nop(); NEXT; }
977 CASE(07) { int c = rlca(); NEXT; }
978 CASE(0F) { int c = rrca(); NEXT; }
979 CASE(17) { int c = rla(); NEXT; }
980 CASE(1F) { int c = rra(); NEXT; }
981 CASE(08) { int c = ex_af_af(); NEXT; }
982 CASE(27) { int c = daa(); NEXT; }
983 CASE(2F) { int c = cpl(); NEXT; }
984 CASE(37) { int c = scf(); NEXT; }
985 CASE(3F) { int c = ccf(); NEXT; }
986 CASE(20) { int c = jr(CondNZ()); NEXT; }
987 CASE(28) { int c = jr(CondZ ()); NEXT; }
988 CASE(30) { int c = jr(CondNC()); NEXT; }
989 CASE(38) { int c = jr(CondC ()); NEXT; }
990 CASE(18) { int c = jr(CondTrue()); NEXT; }
991 CASE(10) { int c = djnz(); NEXT; }
992 CASE(32) { int c = ld_xbyte_a(); NEXT; }
993 CASE(3A) { int c = ld_a_xbyte(); NEXT; }
994 CASE(22) { int c = ld_xword_SS<HL,0>(); NEXT; }
995 CASE(2A) { int c = ld_SS_xword<HL,0>(); NEXT; }
996 CASE(02) { int c = ld_SS_a<BC>(); NEXT; }
997 CASE(12) { int c = ld_SS_a<DE>(); NEXT; }
998 CASE(1A) { int c = ld_a_SS<DE>(); NEXT; }
999 CASE(0A) { int c = ld_a_SS<BC>(); NEXT; }
1000 CASE(03) { int c = inc_SS<BC,0>(); NEXT; }
1001 CASE(13) { int c = inc_SS<DE,0>(); NEXT; }
1002 CASE(23) { int c = inc_SS<HL,0>(); NEXT; }
1003 CASE(33) { int c = inc_SS<SP,0>(); NEXT; }
1004 CASE(0B) { int c = dec_SS<BC,0>(); NEXT; }
1005 CASE(1B) { int c = dec_SS<DE,0>(); NEXT; }
1006 CASE(2B) { int c = dec_SS<HL,0>(); NEXT; }
1007 CASE(3B) { int c = dec_SS<SP,0>(); NEXT; }
1008 CASE(09) { int c = add_SS_TT<HL,BC,0>(); NEXT; }
1009 CASE(19) { int c = add_SS_TT<HL,DE,0>(); NEXT; }
1010 CASE(29) { int c = add_SS_SS<HL ,0>(); NEXT; }
1011 CASE(39) { int c = add_SS_TT<HL,SP,0>(); NEXT; }
1012 CASE(01) { int c = ld_SS_word<BC,0>(); NEXT; }
1013 CASE(11) { int c = ld_SS_word<DE,0>(); NEXT; }
1014 CASE(21) { int c = ld_SS_word<HL,0>(); NEXT; }
1015 CASE(31) { int c = ld_SS_word<SP,0>(); NEXT; }
1016 CASE(04) { int c = inc_R<B,0>(); NEXT; }
1017 CASE(0C) { int c = inc_R<C,0>(); NEXT; }
1018 CASE(14) { int c = inc_R<D,0>(); NEXT; }
1019 CASE(1C) { int c = inc_R<E,0>(); NEXT; }
1020 CASE(24) { int c = inc_R<H,0>(); NEXT; }
1021 CASE(2C) { int c = inc_R<L,0>(); NEXT; }
1022 CASE(3C) { int c = inc_R<A,0>(); NEXT; }
1023 CASE(34) { int c = inc_xhl(); NEXT; }
1024 CASE(05) { int c = dec_R<B,0>(); NEXT; }
1025 CASE(0D) { int c = dec_R<C,0>(); NEXT; }
1026 CASE(15) { int c = dec_R<D,0>(); NEXT; }
1027 CASE(1D) { int c = dec_R<E,0>(); NEXT; }
1028 CASE(25) { int c = dec_R<H,0>(); NEXT; }
1029 CASE(2D) { int c = dec_R<L,0>(); NEXT; }
1030 CASE(3D) { int c = dec_R<A,0>(); NEXT; }
1031 CASE(35) { int c = dec_xhl(); NEXT; }
1032 CASE(06) { int c = ld_R_byte<B,0>(); NEXT; }
1033 CASE(0E) { int c = ld_R_byte<C,0>(); NEXT; }
1034 CASE(16) { int c = ld_R_byte<D,0>(); NEXT; }
1035 CASE(1E) { int c = ld_R_byte<E,0>(); NEXT; }
1036 CASE(26) { int c = ld_R_byte<H,0>(); NEXT; }
1037 CASE(2E) { int c = ld_R_byte<L,0>(); NEXT; }
1038 CASE(3E) { int c = ld_R_byte<A,0>(); NEXT; }
1039 CASE(36) { int c = ld_xhl_byte(); NEXT; }
1040 
1041 CASE(41) { int c = ld_R_R<B,C,0>(); NEXT; }
1042 CASE(42) { int c = ld_R_R<B,D,0>(); NEXT; }
1043 CASE(43) { int c = ld_R_R<B,E,0>(); NEXT; }
1044 CASE(44) { int c = ld_R_R<B,H,0>(); NEXT; }
1045 CASE(45) { int c = ld_R_R<B,L,0>(); NEXT; }
1046 CASE(47) { int c = ld_R_R<B,A,0>(); NEXT; }
1047 CASE(48) { int c = ld_R_R<C,B,0>(); NEXT; }
1048 CASE(4A) { int c = ld_R_R<C,D,0>(); NEXT; }
1049 CASE(4B) { int c = ld_R_R<C,E,0>(); NEXT; }
1050 CASE(4C) { int c = ld_R_R<C,H,0>(); NEXT; }
1051 CASE(4D) { int c = ld_R_R<C,L,0>(); NEXT; }
1052 CASE(4F) { int c = ld_R_R<C,A,0>(); NEXT; }
1053 CASE(50) { int c = ld_R_R<D,B,0>(); NEXT; }
1054 CASE(51) { int c = ld_R_R<D,C,0>(); NEXT; }
1055 CASE(53) { int c = ld_R_R<D,E,0>(); NEXT; }
1056 CASE(54) { int c = ld_R_R<D,H,0>(); NEXT; }
1057 CASE(55) { int c = ld_R_R<D,L,0>(); NEXT; }
1058 CASE(57) { int c = ld_R_R<D,A,0>(); NEXT; }
1059 CASE(58) { int c = ld_R_R<E,B,0>(); NEXT; }
1060 CASE(59) { int c = ld_R_R<E,C,0>(); NEXT; }
1061 CASE(5A) { int c = ld_R_R<E,D,0>(); NEXT; }
1062 CASE(5C) { int c = ld_R_R<E,H,0>(); NEXT; }
1063 CASE(5D) { int c = ld_R_R<E,L,0>(); NEXT; }
1064 CASE(5F) { int c = ld_R_R<E,A,0>(); NEXT; }
1065 CASE(60) { int c = ld_R_R<H,B,0>(); NEXT; }
1066 CASE(61) { int c = ld_R_R<H,C,0>(); NEXT; }
1067 CASE(62) { int c = ld_R_R<H,D,0>(); NEXT; }
1068 CASE(63) { int c = ld_R_R<H,E,0>(); NEXT; }
1069 CASE(65) { int c = ld_R_R<H,L,0>(); NEXT; }
1070 CASE(67) { int c = ld_R_R<H,A,0>(); NEXT; }
1071 CASE(68) { int c = ld_R_R<L,B,0>(); NEXT; }
1072 CASE(69) { int c = ld_R_R<L,C,0>(); NEXT; }
1073 CASE(6A) { int c = ld_R_R<L,D,0>(); NEXT; }
1074 CASE(6B) { int c = ld_R_R<L,E,0>(); NEXT; }
1075 CASE(6C) { int c = ld_R_R<L,H,0>(); NEXT; }
1076 CASE(6F) { int c = ld_R_R<L,A,0>(); NEXT; }
1077 CASE(78) { int c = ld_R_R<A,B,0>(); NEXT; }
1078 CASE(79) { int c = ld_R_R<A,C,0>(); NEXT; }
1079 CASE(7A) { int c = ld_R_R<A,D,0>(); NEXT; }
1080 CASE(7B) { int c = ld_R_R<A,E,0>(); NEXT; }
1081 CASE(7C) { int c = ld_R_R<A,H,0>(); NEXT; }
1082 CASE(7D) { int c = ld_R_R<A,L,0>(); NEXT; }
1083 CASE(70) { int c = ld_xhl_R<B>(); NEXT; }
1084 CASE(71) { int c = ld_xhl_R<C>(); NEXT; }
1085 CASE(72) { int c = ld_xhl_R<D>(); NEXT; }
1086 CASE(73) { int c = ld_xhl_R<E>(); NEXT; }
1087 CASE(74) { int c = ld_xhl_R<H>(); NEXT; }
1088 CASE(75) { int c = ld_xhl_R<L>(); NEXT; }
1089 CASE(77) { int c = ld_xhl_R<A>(); NEXT; }
1090 CASE(46) { int c = ld_R_xhl<B>(); NEXT; }
1091 CASE(4E) { int c = ld_R_xhl<C>(); NEXT; }
1092 CASE(56) { int c = ld_R_xhl<D>(); NEXT; }
1093 CASE(5E) { int c = ld_R_xhl<E>(); NEXT; }
1094 CASE(66) { int c = ld_R_xhl<H>(); NEXT; }
1095 CASE(6E) { int c = ld_R_xhl<L>(); NEXT; }
1096 CASE(7E) { int c = ld_R_xhl<A>(); NEXT; }
1097 CASE(76) { int c = halt(); NEXT_STOP; }
1098 
1099 CASE(80) { int c = add_a_R<B,0>(); NEXT; }
1100 CASE(81) { int c = add_a_R<C,0>(); NEXT; }
1101 CASE(82) { int c = add_a_R<D,0>(); NEXT; }
1102 CASE(83) { int c = add_a_R<E,0>(); NEXT; }
1103 CASE(84) { int c = add_a_R<H,0>(); NEXT; }
1104 CASE(85) { int c = add_a_R<L,0>(); NEXT; }
1105 CASE(86) { int c = add_a_xhl(); NEXT; }
1106 CASE(87) { int c = add_a_a(); NEXT; }
1107 CASE(88) { int c = adc_a_R<B,0>(); NEXT; }
1108 CASE(89) { int c = adc_a_R<C,0>(); NEXT; }
1109 CASE(8A) { int c = adc_a_R<D,0>(); NEXT; }
1110 CASE(8B) { int c = adc_a_R<E,0>(); NEXT; }
1111 CASE(8C) { int c = adc_a_R<H,0>(); NEXT; }
1112 CASE(8D) { int c = adc_a_R<L,0>(); NEXT; }
1113 CASE(8E) { int c = adc_a_xhl(); NEXT; }
1114 CASE(8F) { int c = adc_a_a(); NEXT; }
1115 CASE(90) { int c = sub_R<B,0>(); NEXT; }
1116 CASE(91) { int c = sub_R<C,0>(); NEXT; }
1117 CASE(92) { int c = sub_R<D,0>(); NEXT; }
1118 CASE(93) { int c = sub_R<E,0>(); NEXT; }
1119 CASE(94) { int c = sub_R<H,0>(); NEXT; }
1120 CASE(95) { int c = sub_R<L,0>(); NEXT; }
1121 CASE(96) { int c = sub_xhl(); NEXT; }
1122 CASE(97) { int c = sub_a(); NEXT; }
1123 CASE(98) { int c = sbc_a_R<B,0>(); NEXT; }
1124 CASE(99) { int c = sbc_a_R<C,0>(); NEXT; }
1125 CASE(9A) { int c = sbc_a_R<D,0>(); NEXT; }
1126 CASE(9B) { int c = sbc_a_R<E,0>(); NEXT; }
1127 CASE(9C) { int c = sbc_a_R<H,0>(); NEXT; }
1128 CASE(9D) { int c = sbc_a_R<L,0>(); NEXT; }
1129 CASE(9E) { int c = sbc_a_xhl(); NEXT; }
1130 CASE(9F) { int c = sbc_a_a(); NEXT; }
1131 CASE(A0) { int c = and_R<B,0>(); NEXT; }
1132 CASE(A1) { int c = and_R<C,0>(); NEXT; }
1133 CASE(A2) { int c = and_R<D,0>(); NEXT; }
1134 CASE(A3) { int c = and_R<E,0>(); NEXT; }
1135 CASE(A4) { int c = and_R<H,0>(); NEXT; }
1136 CASE(A5) { int c = and_R<L,0>(); NEXT; }
1137 CASE(A6) { int c = and_xhl(); NEXT; }
1138 CASE(A7) { int c = and_a(); NEXT; }
1139 CASE(A8) { int c = xor_R<B,0>(); NEXT; }
1140 CASE(A9) { int c = xor_R<C,0>(); NEXT; }
1141 CASE(AA) { int c = xor_R<D,0>(); NEXT; }
1142 CASE(AB) { int c = xor_R<E,0>(); NEXT; }
1143 CASE(AC) { int c = xor_R<H,0>(); NEXT; }
1144 CASE(AD) { int c = xor_R<L,0>(); NEXT; }
1145 CASE(AE) { int c = xor_xhl(); NEXT; }
1146 CASE(AF) { int c = xor_a(); NEXT; }
1147 CASE(B0) { int c = or_R<B,0>(); NEXT; }
1148 CASE(B1) { int c = or_R<C,0>(); NEXT; }
1149 CASE(B2) { int c = or_R<D,0>(); NEXT; }
1150 CASE(B3) { int c = or_R<E,0>(); NEXT; }
1151 CASE(B4) { int c = or_R<H,0>(); NEXT; }
1152 CASE(B5) { int c = or_R<L,0>(); NEXT; }
1153 CASE(B6) { int c = or_xhl(); NEXT; }
1154 CASE(B7) { int c = or_a(); NEXT; }
1155 CASE(B8) { int c = cp_R<B,0>(); NEXT; }
1156 CASE(B9) { int c = cp_R<C,0>(); NEXT; }
1157 CASE(BA) { int c = cp_R<D,0>(); NEXT; }
1158 CASE(BB) { int c = cp_R<E,0>(); NEXT; }
1159 CASE(BC) { int c = cp_R<H,0>(); NEXT; }
1160 CASE(BD) { int c = cp_R<L,0>(); NEXT; }
1161 CASE(BE) { int c = cp_xhl(); NEXT; }
1162 CASE(BF) { int c = cp_a(); NEXT; }
1163 
1164 CASE(D3) { int c = out_byte_a(); NEXT; }
1165 CASE(DB) { int c = in_a_byte(); NEXT; }
1166 CASE(D9) { int c = exx(); NEXT; }
1167 CASE(E3) { int c = ex_xsp_SS<HL,0>(); NEXT; }
1168 CASE(EB) { int c = ex_de_hl(); NEXT; }
1169 CASE(E9) { int c = jp_SS<HL,0>(); NEXT; }
1170 CASE(F9) { int c = ld_sp_SS<HL,0>(); NEXT; }
1171 CASE(F3) { int c = di(); NEXT; }
1172 CASE(FB) { int c = ei(); NEXT_EI; }
1173 CASE(C6) { int c = add_a_byte(); NEXT; }
1174 CASE(CE) { int c = adc_a_byte(); NEXT; }
1175 CASE(D6) { int c = sub_byte(); NEXT; }
1176 CASE(DE) { int c = sbc_a_byte(); NEXT; }
1177 CASE(E6) { int c = and_byte(); NEXT; }
1178 CASE(EE) { int c = xor_byte(); NEXT; }
1179 CASE(F6) { int c = or_byte(); NEXT; }
1180 CASE(FE) { int c = cp_byte(); NEXT; }
1181 CASE(C0) { int c = ret(CondNZ()); NEXT; }
1182 CASE(C8) { int c = ret(CondZ ()); NEXT; }
1183 CASE(D0) { int c = ret(CondNC()); NEXT; }
1184 CASE(D8) { int c = ret(CondC ()); NEXT; }
1185 CASE(E0) { int c = ret(CondPO()); NEXT; }
1186 CASE(E8) { int c = ret(CondPE()); NEXT; }
1187 CASE(F0) { int c = ret(CondP ()); NEXT; }
1188 CASE(F8) { int c = ret(CondM ()); NEXT; }
1189 CASE(C9) { int c = ret(); NEXT; }
1190 CASE(C2) { int c = jp(CondNZ()); NEXT; }
1191 CASE(CA) { int c = jp(CondZ ()); NEXT; }
1192 CASE(D2) { int c = jp(CondNC()); NEXT; }
1193 CASE(DA) { int c = jp(CondC ()); NEXT; }
1194 CASE(E2) { int c = jp(CondPO()); NEXT; }
1195 CASE(EA) { int c = jp(CondPE()); NEXT; }
1196 CASE(F2) { int c = jp(CondP ()); NEXT; }
1197 CASE(FA) { int c = jp(CondM ()); NEXT; }
1198 CASE(C3) { int c = jp(CondTrue()); NEXT; }
1199 CASE(C4) { int c = call(CondNZ()); NEXT; }
1200 CASE(CC) { int c = call(CondZ ()); NEXT; }
1201 CASE(D4) { int c = call(CondNC()); NEXT; }
1202 CASE(DC) { int c = call(CondC ()); NEXT; }
1203 CASE(E4) { int c = call(CondPO()); NEXT; }
1204 CASE(EC) { int c = call(CondPE()); NEXT; }
1205 CASE(F4) { int c = call(CondP ()); NEXT; }
1206 CASE(FC) { int c = call(CondM ()); NEXT; }
1207 CASE(CD) { int c = call(CondTrue()); NEXT; }
1208 CASE(C1) { int c = pop_SS <BC,0>(); NEXT; }
1209 CASE(D1) { int c = pop_SS <DE,0>(); NEXT; }
1210 CASE(E1) { int c = pop_SS <HL,0>(); NEXT; }
1211 CASE(F1) { int c = pop_SS <AF,0>(); NEXT; }
1212 CASE(C5) { int c = push_SS<BC,0>(); NEXT; }
1213 CASE(D5) { int c = push_SS<DE,0>(); NEXT; }
1214 CASE(E5) { int c = push_SS<HL,0>(); NEXT; }
1215 CASE(F5) { int c = push_SS<AF,0>(); NEXT; }
1216 CASE(C7) { int c = rst<0x00>(); NEXT; }
1217 CASE(CF) { int c = rst<0x08>(); NEXT; }
1218 CASE(D7) { int c = rst<0x10>(); NEXT; }
1219 CASE(DF) { int c = rst<0x18>(); NEXT; }
1220 CASE(E7) { int c = rst<0x20>(); NEXT; }
1221 CASE(EF) { int c = rst<0x28>(); NEXT; }
1222 CASE(F7) { int c = rst<0x30>(); NEXT; }
1223 CASE(FF) { int c = rst<0x38>(); NEXT; }
1224 CASE(CB) {
1225  byte cb_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1226  incR(1);
1227  switch (cb_opcode) {
1228  case 0x00: { int c = rlc_R<B>(); NEXT; }
1229  case 0x01: { int c = rlc_R<C>(); NEXT; }
1230  case 0x02: { int c = rlc_R<D>(); NEXT; }
1231  case 0x03: { int c = rlc_R<E>(); NEXT; }
1232  case 0x04: { int c = rlc_R<H>(); NEXT; }
1233  case 0x05: { int c = rlc_R<L>(); NEXT; }
1234  case 0x07: { int c = rlc_R<A>(); NEXT; }
1235  case 0x06: { int c = rlc_xhl(); NEXT; }
1236  case 0x08: { int c = rrc_R<B>(); NEXT; }
1237  case 0x09: { int c = rrc_R<C>(); NEXT; }
1238  case 0x0a: { int c = rrc_R<D>(); NEXT; }
1239  case 0x0b: { int c = rrc_R<E>(); NEXT; }
1240  case 0x0c: { int c = rrc_R<H>(); NEXT; }
1241  case 0x0d: { int c = rrc_R<L>(); NEXT; }
1242  case 0x0f: { int c = rrc_R<A>(); NEXT; }
1243  case 0x0e: { int c = rrc_xhl(); NEXT; }
1244  case 0x10: { int c = rl_R<B>(); NEXT; }
1245  case 0x11: { int c = rl_R<C>(); NEXT; }
1246  case 0x12: { int c = rl_R<D>(); NEXT; }
1247  case 0x13: { int c = rl_R<E>(); NEXT; }
1248  case 0x14: { int c = rl_R<H>(); NEXT; }
1249  case 0x15: { int c = rl_R<L>(); NEXT; }
1250  case 0x17: { int c = rl_R<A>(); NEXT; }
1251  case 0x16: { int c = rl_xhl(); NEXT; }
1252  case 0x18: { int c = rr_R<B>(); NEXT; }
1253  case 0x19: { int c = rr_R<C>(); NEXT; }
1254  case 0x1a: { int c = rr_R<D>(); NEXT; }
1255  case 0x1b: { int c = rr_R<E>(); NEXT; }
1256  case 0x1c: { int c = rr_R<H>(); NEXT; }
1257  case 0x1d: { int c = rr_R<L>(); NEXT; }
1258  case 0x1f: { int c = rr_R<A>(); NEXT; }
1259  case 0x1e: { int c = rr_xhl(); NEXT; }
1260  case 0x20: { int c = sla_R<B>(); NEXT; }
1261  case 0x21: { int c = sla_R<C>(); NEXT; }
1262  case 0x22: { int c = sla_R<D>(); NEXT; }
1263  case 0x23: { int c = sla_R<E>(); NEXT; }
1264  case 0x24: { int c = sla_R<H>(); NEXT; }
1265  case 0x25: { int c = sla_R<L>(); NEXT; }
1266  case 0x27: { int c = sla_R<A>(); NEXT; }
1267  case 0x26: { int c = sla_xhl(); NEXT; }
1268  case 0x28: { int c = sra_R<B>(); NEXT; }
1269  case 0x29: { int c = sra_R<C>(); NEXT; }
1270  case 0x2a: { int c = sra_R<D>(); NEXT; }
1271  case 0x2b: { int c = sra_R<E>(); NEXT; }
1272  case 0x2c: { int c = sra_R<H>(); NEXT; }
1273  case 0x2d: { int c = sra_R<L>(); NEXT; }
1274  case 0x2f: { int c = sra_R<A>(); NEXT; }
1275  case 0x2e: { int c = sra_xhl(); NEXT; }
1276  case 0x30: { int c = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1277  case 0x31: { int c = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1278  case 0x32: { int c = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1279  case 0x33: { int c = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1280  case 0x34: { int c = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1281  case 0x35: { int c = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1282  case 0x37: { int c = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1283  case 0x36: { int c = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1284  case 0x38: { int c = srl_R<B>(); NEXT; }
1285  case 0x39: { int c = srl_R<C>(); NEXT; }
1286  case 0x3a: { int c = srl_R<D>(); NEXT; }
1287  case 0x3b: { int c = srl_R<E>(); NEXT; }
1288  case 0x3c: { int c = srl_R<H>(); NEXT; }
1289  case 0x3d: { int c = srl_R<L>(); NEXT; }
1290  case 0x3f: { int c = srl_R<A>(); NEXT; }
1291  case 0x3e: { int c = srl_xhl(); NEXT; }
1292 
1293  case 0x40: { int c = bit_N_R<0,B>(); NEXT; }
1294  case 0x41: { int c = bit_N_R<0,C>(); NEXT; }
1295  case 0x42: { int c = bit_N_R<0,D>(); NEXT; }
1296  case 0x43: { int c = bit_N_R<0,E>(); NEXT; }
1297  case 0x44: { int c = bit_N_R<0,H>(); NEXT; }
1298  case 0x45: { int c = bit_N_R<0,L>(); NEXT; }
1299  case 0x47: { int c = bit_N_R<0,A>(); NEXT; }
1300  case 0x48: { int c = bit_N_R<1,B>(); NEXT; }
1301  case 0x49: { int c = bit_N_R<1,C>(); NEXT; }
1302  case 0x4a: { int c = bit_N_R<1,D>(); NEXT; }
1303  case 0x4b: { int c = bit_N_R<1,E>(); NEXT; }
1304  case 0x4c: { int c = bit_N_R<1,H>(); NEXT; }
1305  case 0x4d: { int c = bit_N_R<1,L>(); NEXT; }
1306  case 0x4f: { int c = bit_N_R<1,A>(); NEXT; }
1307  case 0x50: { int c = bit_N_R<2,B>(); NEXT; }
1308  case 0x51: { int c = bit_N_R<2,C>(); NEXT; }
1309  case 0x52: { int c = bit_N_R<2,D>(); NEXT; }
1310  case 0x53: { int c = bit_N_R<2,E>(); NEXT; }
1311  case 0x54: { int c = bit_N_R<2,H>(); NEXT; }
1312  case 0x55: { int c = bit_N_R<2,L>(); NEXT; }
1313  case 0x57: { int c = bit_N_R<2,A>(); NEXT; }
1314  case 0x58: { int c = bit_N_R<3,B>(); NEXT; }
1315  case 0x59: { int c = bit_N_R<3,C>(); NEXT; }
1316  case 0x5a: { int c = bit_N_R<3,D>(); NEXT; }
1317  case 0x5b: { int c = bit_N_R<3,E>(); NEXT; }
1318  case 0x5c: { int c = bit_N_R<3,H>(); NEXT; }
1319  case 0x5d: { int c = bit_N_R<3,L>(); NEXT; }
1320  case 0x5f: { int c = bit_N_R<3,A>(); NEXT; }
1321  case 0x60: { int c = bit_N_R<4,B>(); NEXT; }
1322  case 0x61: { int c = bit_N_R<4,C>(); NEXT; }
1323  case 0x62: { int c = bit_N_R<4,D>(); NEXT; }
1324  case 0x63: { int c = bit_N_R<4,E>(); NEXT; }
1325  case 0x64: { int c = bit_N_R<4,H>(); NEXT; }
1326  case 0x65: { int c = bit_N_R<4,L>(); NEXT; }
1327  case 0x67: { int c = bit_N_R<4,A>(); NEXT; }
1328  case 0x68: { int c = bit_N_R<5,B>(); NEXT; }
1329  case 0x69: { int c = bit_N_R<5,C>(); NEXT; }
1330  case 0x6a: { int c = bit_N_R<5,D>(); NEXT; }
1331  case 0x6b: { int c = bit_N_R<5,E>(); NEXT; }
1332  case 0x6c: { int c = bit_N_R<5,H>(); NEXT; }
1333  case 0x6d: { int c = bit_N_R<5,L>(); NEXT; }
1334  case 0x6f: { int c = bit_N_R<5,A>(); NEXT; }
1335  case 0x70: { int c = bit_N_R<6,B>(); NEXT; }
1336  case 0x71: { int c = bit_N_R<6,C>(); NEXT; }
1337  case 0x72: { int c = bit_N_R<6,D>(); NEXT; }
1338  case 0x73: { int c = bit_N_R<6,E>(); NEXT; }
1339  case 0x74: { int c = bit_N_R<6,H>(); NEXT; }
1340  case 0x75: { int c = bit_N_R<6,L>(); NEXT; }
1341  case 0x77: { int c = bit_N_R<6,A>(); NEXT; }
1342  case 0x78: { int c = bit_N_R<7,B>(); NEXT; }
1343  case 0x79: { int c = bit_N_R<7,C>(); NEXT; }
1344  case 0x7a: { int c = bit_N_R<7,D>(); NEXT; }
1345  case 0x7b: { int c = bit_N_R<7,E>(); NEXT; }
1346  case 0x7c: { int c = bit_N_R<7,H>(); NEXT; }
1347  case 0x7d: { int c = bit_N_R<7,L>(); NEXT; }
1348  case 0x7f: { int c = bit_N_R<7,A>(); NEXT; }
1349  case 0x46: { int c = bit_N_xhl<0>(); NEXT; }
1350  case 0x4e: { int c = bit_N_xhl<1>(); NEXT; }
1351  case 0x56: { int c = bit_N_xhl<2>(); NEXT; }
1352  case 0x5e: { int c = bit_N_xhl<3>(); NEXT; }
1353  case 0x66: { int c = bit_N_xhl<4>(); NEXT; }
1354  case 0x6e: { int c = bit_N_xhl<5>(); NEXT; }
1355  case 0x76: { int c = bit_N_xhl<6>(); NEXT; }
1356  case 0x7e: { int c = bit_N_xhl<7>(); NEXT; }
1357 
1358  case 0x80: { int c = res_N_R<0,B>(); NEXT; }
1359  case 0x81: { int c = res_N_R<0,C>(); NEXT; }
1360  case 0x82: { int c = res_N_R<0,D>(); NEXT; }
1361  case 0x83: { int c = res_N_R<0,E>(); NEXT; }
1362  case 0x84: { int c = res_N_R<0,H>(); NEXT; }
1363  case 0x85: { int c = res_N_R<0,L>(); NEXT; }
1364  case 0x87: { int c = res_N_R<0,A>(); NEXT; }
1365  case 0x88: { int c = res_N_R<1,B>(); NEXT; }
1366  case 0x89: { int c = res_N_R<1,C>(); NEXT; }
1367  case 0x8a: { int c = res_N_R<1,D>(); NEXT; }
1368  case 0x8b: { int c = res_N_R<1,E>(); NEXT; }
1369  case 0x8c: { int c = res_N_R<1,H>(); NEXT; }
1370  case 0x8d: { int c = res_N_R<1,L>(); NEXT; }
1371  case 0x8f: { int c = res_N_R<1,A>(); NEXT; }
1372  case 0x90: { int c = res_N_R<2,B>(); NEXT; }
1373  case 0x91: { int c = res_N_R<2,C>(); NEXT; }
1374  case 0x92: { int c = res_N_R<2,D>(); NEXT; }
1375  case 0x93: { int c = res_N_R<2,E>(); NEXT; }
1376  case 0x94: { int c = res_N_R<2,H>(); NEXT; }
1377  case 0x95: { int c = res_N_R<2,L>(); NEXT; }
1378  case 0x97: { int c = res_N_R<2,A>(); NEXT; }
1379  case 0x98: { int c = res_N_R<3,B>(); NEXT; }
1380  case 0x99: { int c = res_N_R<3,C>(); NEXT; }
1381  case 0x9a: { int c = res_N_R<3,D>(); NEXT; }
1382  case 0x9b: { int c = res_N_R<3,E>(); NEXT; }
1383  case 0x9c: { int c = res_N_R<3,H>(); NEXT; }
1384  case 0x9d: { int c = res_N_R<3,L>(); NEXT; }
1385  case 0x9f: { int c = res_N_R<3,A>(); NEXT; }
1386  case 0xa0: { int c = res_N_R<4,B>(); NEXT; }
1387  case 0xa1: { int c = res_N_R<4,C>(); NEXT; }
1388  case 0xa2: { int c = res_N_R<4,D>(); NEXT; }
1389  case 0xa3: { int c = res_N_R<4,E>(); NEXT; }
1390  case 0xa4: { int c = res_N_R<4,H>(); NEXT; }
1391  case 0xa5: { int c = res_N_R<4,L>(); NEXT; }
1392  case 0xa7: { int c = res_N_R<4,A>(); NEXT; }
1393  case 0xa8: { int c = res_N_R<5,B>(); NEXT; }
1394  case 0xa9: { int c = res_N_R<5,C>(); NEXT; }
1395  case 0xaa: { int c = res_N_R<5,D>(); NEXT; }
1396  case 0xab: { int c = res_N_R<5,E>(); NEXT; }
1397  case 0xac: { int c = res_N_R<5,H>(); NEXT; }
1398  case 0xad: { int c = res_N_R<5,L>(); NEXT; }
1399  case 0xaf: { int c = res_N_R<5,A>(); NEXT; }
1400  case 0xb0: { int c = res_N_R<6,B>(); NEXT; }
1401  case 0xb1: { int c = res_N_R<6,C>(); NEXT; }
1402  case 0xb2: { int c = res_N_R<6,D>(); NEXT; }
1403  case 0xb3: { int c = res_N_R<6,E>(); NEXT; }
1404  case 0xb4: { int c = res_N_R<6,H>(); NEXT; }
1405  case 0xb5: { int c = res_N_R<6,L>(); NEXT; }
1406  case 0xb7: { int c = res_N_R<6,A>(); NEXT; }
1407  case 0xb8: { int c = res_N_R<7,B>(); NEXT; }
1408  case 0xb9: { int c = res_N_R<7,C>(); NEXT; }
1409  case 0xba: { int c = res_N_R<7,D>(); NEXT; }
1410  case 0xbb: { int c = res_N_R<7,E>(); NEXT; }
1411  case 0xbc: { int c = res_N_R<7,H>(); NEXT; }
1412  case 0xbd: { int c = res_N_R<7,L>(); NEXT; }
1413  case 0xbf: { int c = res_N_R<7,A>(); NEXT; }
1414  case 0x86: { int c = res_N_xhl<0>(); NEXT; }
1415  case 0x8e: { int c = res_N_xhl<1>(); NEXT; }
1416  case 0x96: { int c = res_N_xhl<2>(); NEXT; }
1417  case 0x9e: { int c = res_N_xhl<3>(); NEXT; }
1418  case 0xa6: { int c = res_N_xhl<4>(); NEXT; }
1419  case 0xae: { int c = res_N_xhl<5>(); NEXT; }
1420  case 0xb6: { int c = res_N_xhl<6>(); NEXT; }
1421  case 0xbe: { int c = res_N_xhl<7>(); NEXT; }
1422 
1423  case 0xc0: { int c = set_N_R<0,B>(); NEXT; }
1424  case 0xc1: { int c = set_N_R<0,C>(); NEXT; }
1425  case 0xc2: { int c = set_N_R<0,D>(); NEXT; }
1426  case 0xc3: { int c = set_N_R<0,E>(); NEXT; }
1427  case 0xc4: { int c = set_N_R<0,H>(); NEXT; }
1428  case 0xc5: { int c = set_N_R<0,L>(); NEXT; }
1429  case 0xc7: { int c = set_N_R<0,A>(); NEXT; }
1430  case 0xc8: { int c = set_N_R<1,B>(); NEXT; }
1431  case 0xc9: { int c = set_N_R<1,C>(); NEXT; }
1432  case 0xca: { int c = set_N_R<1,D>(); NEXT; }
1433  case 0xcb: { int c = set_N_R<1,E>(); NEXT; }
1434  case 0xcc: { int c = set_N_R<1,H>(); NEXT; }
1435  case 0xcd: { int c = set_N_R<1,L>(); NEXT; }
1436  case 0xcf: { int c = set_N_R<1,A>(); NEXT; }
1437  case 0xd0: { int c = set_N_R<2,B>(); NEXT; }
1438  case 0xd1: { int c = set_N_R<2,C>(); NEXT; }
1439  case 0xd2: { int c = set_N_R<2,D>(); NEXT; }
1440  case 0xd3: { int c = set_N_R<2,E>(); NEXT; }
1441  case 0xd4: { int c = set_N_R<2,H>(); NEXT; }
1442  case 0xd5: { int c = set_N_R<2,L>(); NEXT; }
1443  case 0xd7: { int c = set_N_R<2,A>(); NEXT; }
1444  case 0xd8: { int c = set_N_R<3,B>(); NEXT; }
1445  case 0xd9: { int c = set_N_R<3,C>(); NEXT; }
1446  case 0xda: { int c = set_N_R<3,D>(); NEXT; }
1447  case 0xdb: { int c = set_N_R<3,E>(); NEXT; }
1448  case 0xdc: { int c = set_N_R<3,H>(); NEXT; }
1449  case 0xdd: { int c = set_N_R<3,L>(); NEXT; }
1450  case 0xdf: { int c = set_N_R<3,A>(); NEXT; }
1451  case 0xe0: { int c = set_N_R<4,B>(); NEXT; }
1452  case 0xe1: { int c = set_N_R<4,C>(); NEXT; }
1453  case 0xe2: { int c = set_N_R<4,D>(); NEXT; }
1454  case 0xe3: { int c = set_N_R<4,E>(); NEXT; }
1455  case 0xe4: { int c = set_N_R<4,H>(); NEXT; }
1456  case 0xe5: { int c = set_N_R<4,L>(); NEXT; }
1457  case 0xe7: { int c = set_N_R<4,A>(); NEXT; }
1458  case 0xe8: { int c = set_N_R<5,B>(); NEXT; }
1459  case 0xe9: { int c = set_N_R<5,C>(); NEXT; }
1460  case 0xea: { int c = set_N_R<5,D>(); NEXT; }
1461  case 0xeb: { int c = set_N_R<5,E>(); NEXT; }
1462  case 0xec: { int c = set_N_R<5,H>(); NEXT; }
1463  case 0xed: { int c = set_N_R<5,L>(); NEXT; }
1464  case 0xef: { int c = set_N_R<5,A>(); NEXT; }
1465  case 0xf0: { int c = set_N_R<6,B>(); NEXT; }
1466  case 0xf1: { int c = set_N_R<6,C>(); NEXT; }
1467  case 0xf2: { int c = set_N_R<6,D>(); NEXT; }
1468  case 0xf3: { int c = set_N_R<6,E>(); NEXT; }
1469  case 0xf4: { int c = set_N_R<6,H>(); NEXT; }
1470  case 0xf5: { int c = set_N_R<6,L>(); NEXT; }
1471  case 0xf7: { int c = set_N_R<6,A>(); NEXT; }
1472  case 0xf8: { int c = set_N_R<7,B>(); NEXT; }
1473  case 0xf9: { int c = set_N_R<7,C>(); NEXT; }
1474  case 0xfa: { int c = set_N_R<7,D>(); NEXT; }
1475  case 0xfb: { int c = set_N_R<7,E>(); NEXT; }
1476  case 0xfc: { int c = set_N_R<7,H>(); NEXT; }
1477  case 0xfd: { int c = set_N_R<7,L>(); NEXT; }
1478  case 0xff: { int c = set_N_R<7,A>(); NEXT; }
1479  case 0xc6: { int c = set_N_xhl<0>(); NEXT; }
1480  case 0xce: { int c = set_N_xhl<1>(); NEXT; }
1481  case 0xd6: { int c = set_N_xhl<2>(); NEXT; }
1482  case 0xde: { int c = set_N_xhl<3>(); NEXT; }
1483  case 0xe6: { int c = set_N_xhl<4>(); NEXT; }
1484  case 0xee: { int c = set_N_xhl<5>(); NEXT; }
1485  case 0xf6: { int c = set_N_xhl<6>(); NEXT; }
1486  case 0xfe: { int c = set_N_xhl<7>(); NEXT; }
1487  default: UNREACHABLE; return;
1488  }
1489 }
1490 CASE(ED) {
1491  byte ed_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1492  incR(1);
1493  switch (ed_opcode) {
1494  case 0x00: case 0x01: case 0x02: case 0x03:
1495  case 0x04: case 0x05: case 0x06: case 0x07:
1496  case 0x08: case 0x09: case 0x0a: case 0x0b:
1497  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1498  case 0x10: case 0x11: case 0x12: case 0x13:
1499  case 0x14: case 0x15: case 0x16: case 0x17:
1500  case 0x18: case 0x19: case 0x1a: case 0x1b:
1501  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1502  case 0x20: case 0x21: case 0x22: case 0x23:
1503  case 0x24: case 0x25: case 0x26: case 0x27:
1504  case 0x28: case 0x29: case 0x2a: case 0x2b:
1505  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1506  case 0x30: case 0x31: case 0x32: case 0x33:
1507  case 0x34: case 0x35: case 0x36: case 0x37:
1508  case 0x38: case 0x39: case 0x3a: case 0x3b:
1509  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1510 
1511  case 0x77: case 0x7f:
1512 
1513  case 0x80: case 0x81: case 0x82: case 0x83:
1514  case 0x84: case 0x85: case 0x86: case 0x87:
1515  case 0x88: case 0x89: case 0x8a: case 0x8b:
1516  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1517  case 0x90: case 0x91: case 0x92: case 0x93:
1518  case 0x94: case 0x95: case 0x96: case 0x97:
1519  case 0x98: case 0x99: case 0x9a: case 0x9b:
1520  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1521  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1522  case 0xac: case 0xad: case 0xae: case 0xaf:
1523  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1524  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1525 
1526  case 0xc0: case 0xc2:
1527  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1528  case 0xc8: case 0xca: case 0xcb:
1529  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1530  case 0xd0: case 0xd2: case 0xd3:
1531  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1532  case 0xd8: case 0xda: case 0xdb:
1533  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1534  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1535  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1536  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1537  case 0xec: case 0xed: case 0xee: case 0xef:
1538  case 0xf0: case 0xf1: case 0xf2:
1539  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1540  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1541  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1542  { int c = nop(); NEXT; }
1543 
1544  case 0x40: { int c = in_R_c<B>(); NEXT; }
1545  case 0x48: { int c = in_R_c<C>(); NEXT; }
1546  case 0x50: { int c = in_R_c<D>(); NEXT; }
1547  case 0x58: { int c = in_R_c<E>(); NEXT; }
1548  case 0x60: { int c = in_R_c<H>(); NEXT; }
1549  case 0x68: { int c = in_R_c<L>(); NEXT; }
1550  case 0x70: { int c = in_R_c<DUMMY>(); NEXT; }
1551  case 0x78: { int c = in_R_c<A>(); NEXT; }
1552 
1553  case 0x41: { int c = out_c_R<B>(); NEXT; }
1554  case 0x49: { int c = out_c_R<C>(); NEXT; }
1555  case 0x51: { int c = out_c_R<D>(); NEXT; }
1556  case 0x59: { int c = out_c_R<E>(); NEXT; }
1557  case 0x61: { int c = out_c_R<H>(); NEXT; }
1558  case 0x69: { int c = out_c_R<L>(); NEXT; }
1559  case 0x71: { int c = out_c_0(); NEXT; }
1560  case 0x79: { int c = out_c_R<A>(); NEXT; }
1561 
1562  case 0x42: { int c = sbc_hl_SS<BC>(); NEXT; }
1563  case 0x52: { int c = sbc_hl_SS<DE>(); NEXT; }
1564  case 0x62: { int c = sbc_hl_hl (); NEXT; }
1565  case 0x72: { int c = sbc_hl_SS<SP>(); NEXT; }
1566 
1567  case 0x4a: { int c = adc_hl_SS<BC>(); NEXT; }
1568  case 0x5a: { int c = adc_hl_SS<DE>(); NEXT; }
1569  case 0x6a: { int c = adc_hl_hl (); NEXT; }
1570  case 0x7a: { int c = adc_hl_SS<SP>(); NEXT; }
1571 
1572  case 0x43: { int c = ld_xword_SS_ED<BC>(); NEXT; }
1573  case 0x53: { int c = ld_xword_SS_ED<DE>(); NEXT; }
1574  case 0x63: { int c = ld_xword_SS_ED<HL>(); NEXT; }
1575  case 0x73: { int c = ld_xword_SS_ED<SP>(); NEXT; }
1576 
1577  case 0x4b: { int c = ld_SS_xword_ED<BC>(); NEXT; }
1578  case 0x5b: { int c = ld_SS_xword_ED<DE>(); NEXT; }
1579  case 0x6b: { int c = ld_SS_xword_ED<HL>(); NEXT; }
1580  case 0x7b: { int c = ld_SS_xword_ED<SP>(); NEXT; }
1581 
1582  case 0x47: { int c = ld_i_a(); NEXT; }
1583  case 0x4f: { int c = ld_r_a(); NEXT; }
1584  case 0x57: { int c = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1585  case 0x5f: { int c = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1586 
1587  case 0x67: { int c = rrd(); NEXT; }
1588  case 0x6f: { int c = rld(); NEXT; }
1589 
1590  case 0x45: case 0x4d: case 0x55: case 0x5d:
1591  case 0x65: case 0x6d: case 0x75: case 0x7d:
1592  { int c = retn(); NEXT_STOP; }
1593  case 0x46: case 0x4e: case 0x66: case 0x6e:
1594  { int c = im_N<0>(); NEXT; }
1595  case 0x56: case 0x76:
1596  { int c = im_N<1>(); NEXT; }
1597  case 0x5e: case 0x7e:
1598  { int c = im_N<2>(); NEXT; }
1599  case 0x44: case 0x4c: case 0x54: case 0x5c:
1600  case 0x64: case 0x6c: case 0x74: case 0x7c:
1601  { int c = neg(); NEXT; }
1602 
1603  case 0xa0: { int c = ldi(); NEXT; }
1604  case 0xa1: { int c = cpi(); NEXT; }
1605  case 0xa2: { int c = ini(); NEXT; }
1606  case 0xa3: { int c = outi(); NEXT; }
1607  case 0xa8: { int c = ldd(); NEXT; }
1608  case 0xa9: { int c = cpd(); NEXT; }
1609  case 0xaa: { int c = ind(); NEXT; }
1610  case 0xab: { int c = outd(); NEXT; }
1611  case 0xb0: { int c = ldir(); NEXT; }
1612  case 0xb1: { int c = cpir(); NEXT; }
1613  case 0xb2: { int c = inir(); NEXT; }
1614  case 0xb3: { int c = otir(); NEXT; }
1615  case 0xb8: { int c = lddr(); NEXT; }
1616  case 0xb9: { int c = cpdr(); NEXT; }
1617  case 0xba: { int c = indr(); NEXT; }
1618  case 0xbb: { int c = otdr(); NEXT; }
1619 
1620  case 0xc1: { int c = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1621  case 0xc9: { int c = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1622  case 0xd1: { int c = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1623  case 0xd9: { int c = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1624  case 0xc3: { int c = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1625  case 0xf3: { int c = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1626  default: UNREACHABLE; return;
1627  }
1628 }
1629 opDD_2:
1630 CASE(DD) {
1631  byte opcodeDD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1632  incR(1);
1633  switch (opcodeDD) {
1634  case 0x00: // nop();
1635  case 0x01: // ld_bc_word();
1636  case 0x02: // ld_xbc_a();
1637  case 0x03: // inc_bc();
1638  case 0x04: // inc_b();
1639  case 0x05: // dec_b();
1640  case 0x06: // ld_b_byte();
1641  case 0x07: // rlca();
1642  case 0x08: // ex_af_af();
1643  case 0x0a: // ld_a_xbc();
1644  case 0x0b: // dec_bc();
1645  case 0x0c: // inc_c();
1646  case 0x0d: // dec_c();
1647  case 0x0e: // ld_c_byte();
1648  case 0x0f: // rrca();
1649  case 0x10: // djnz();
1650  case 0x11: // ld_de_word();
1651  case 0x12: // ld_xde_a();
1652  case 0x13: // inc_de();
1653  case 0x14: // inc_d();
1654  case 0x15: // dec_d();
1655  case 0x16: // ld_d_byte();
1656  case 0x17: // rla();
1657  case 0x18: // jr();
1658  case 0x1a: // ld_a_xde();
1659  case 0x1b: // dec_de();
1660  case 0x1c: // inc_e();
1661  case 0x1d: // dec_e();
1662  case 0x1e: // ld_e_byte();
1663  case 0x1f: // rra();
1664  case 0x20: // jr_nz();
1665  case 0x27: // daa();
1666  case 0x28: // jr_z();
1667  case 0x2f: // cpl();
1668  case 0x30: // jr_nc();
1669  case 0x31: // ld_sp_word();
1670  case 0x32: // ld_xbyte_a();
1671  case 0x33: // inc_sp();
1672  case 0x37: // scf();
1673  case 0x38: // jr_c();
1674  case 0x3a: // ld_a_xbyte();
1675  case 0x3b: // dec_sp();
1676  case 0x3c: // inc_a();
1677  case 0x3d: // dec_a();
1678  case 0x3e: // ld_a_byte();
1679  case 0x3f: // ccf();
1680 
1681  case 0x40: // ld_b_b();
1682  case 0x41: // ld_b_c();
1683  case 0x42: // ld_b_d();
1684  case 0x43: // ld_b_e();
1685  case 0x47: // ld_b_a();
1686  case 0x48: // ld_c_b();
1687  case 0x49: // ld_c_c();
1688  case 0x4a: // ld_c_d();
1689  case 0x4b: // ld_c_e();
1690  case 0x4f: // ld_c_a();
1691  case 0x50: // ld_d_b();
1692  case 0x51: // ld_d_c();
1693  case 0x52: // ld_d_d();
1694  case 0x53: // ld_d_e();
1695  case 0x57: // ld_d_a();
1696  case 0x58: // ld_e_b();
1697  case 0x59: // ld_e_c();
1698  case 0x5a: // ld_e_d();
1699  case 0x5b: // ld_e_e();
1700  case 0x5f: // ld_e_a();
1701  case 0x64: // ld_ixh_ixh(); == nop
1702  case 0x6d: // ld_ixl_ixl(); == nop
1703  case 0x76: // halt();
1704  case 0x78: // ld_a_b();
1705  case 0x79: // ld_a_c();
1706  case 0x7a: // ld_a_d();
1707  case 0x7b: // ld_a_e();
1708  case 0x7f: // ld_a_a();
1709 
1710  case 0x80: // add_a_b();
1711  case 0x81: // add_a_c();
1712  case 0x82: // add_a_d();
1713  case 0x83: // add_a_e();
1714  case 0x87: // add_a_a();
1715  case 0x88: // adc_a_b();
1716  case 0x89: // adc_a_c();
1717  case 0x8a: // adc_a_d();
1718  case 0x8b: // adc_a_e();
1719  case 0x8f: // adc_a_a();
1720  case 0x90: // sub_b();
1721  case 0x91: // sub_c();
1722  case 0x92: // sub_d();
1723  case 0x93: // sub_e();
1724  case 0x97: // sub_a();
1725  case 0x98: // sbc_a_b();
1726  case 0x99: // sbc_a_c();
1727  case 0x9a: // sbc_a_d();
1728  case 0x9b: // sbc_a_e();
1729  case 0x9f: // sbc_a_a();
1730  case 0xa0: // and_b();
1731  case 0xa1: // and_c();
1732  case 0xa2: // and_d();
1733  case 0xa3: // and_e();
1734  case 0xa7: // and_a();
1735  case 0xa8: // xor_b();
1736  case 0xa9: // xor_c();
1737  case 0xaa: // xor_d();
1738  case 0xab: // xor_e();
1739  case 0xaf: // xor_a();
1740  case 0xb0: // or_b();
1741  case 0xb1: // or_c();
1742  case 0xb2: // or_d();
1743  case 0xb3: // or_e();
1744  case 0xb7: // or_a();
1745  case 0xb8: // cp_b();
1746  case 0xb9: // cp_c();
1747  case 0xba: // cp_d();
1748  case 0xbb: // cp_e();
1749  case 0xbf: // cp_a();
1750 
1751  case 0xc0: // ret_nz();
1752  case 0xc1: // pop_bc();
1753  case 0xc2: // jp_nz();
1754  case 0xc3: // jp();
1755  case 0xc4: // call_nz();
1756  case 0xc5: // push_bc();
1757  case 0xc6: // add_a_byte();
1758  case 0xc7: // rst_00();
1759  case 0xc8: // ret_z();
1760  case 0xc9: // ret();
1761  case 0xca: // jp_z();
1762  case 0xcc: // call_z();
1763  case 0xcd: // call();
1764  case 0xce: // adc_a_byte();
1765  case 0xcf: // rst_08();
1766  case 0xd0: // ret_nc();
1767  case 0xd1: // pop_de();
1768  case 0xd2: // jp_nc();
1769  case 0xd3: // out_byte_a();
1770  case 0xd4: // call_nc();
1771  case 0xd5: // push_de();
1772  case 0xd6: // sub_byte();
1773  case 0xd7: // rst_10();
1774  case 0xd8: // ret_c();
1775  case 0xd9: // exx();
1776  case 0xda: // jp_c();
1777  case 0xdb: // in_a_byte();
1778  case 0xdc: // call_c();
1779  case 0xde: // sbc_a_byte();
1780  case 0xdf: // rst_18();
1781  case 0xe0: // ret_po();
1782  case 0xe2: // jp_po();
1783  case 0xe4: // call_po();
1784  case 0xe6: // and_byte();
1785  case 0xe7: // rst_20();
1786  case 0xe8: // ret_pe();
1787  case 0xea: // jp_pe();
1788  case 0xeb: // ex_de_hl();
1789  case 0xec: // call_pe();
1790  case 0xed: // ed();
1791  case 0xee: // xor_byte();
1792  case 0xef: // rst_28();
1793  case 0xf0: // ret_p();
1794  case 0xf1: // pop_af();
1795  case 0xf2: // jp_p();
1796  case 0xf3: // di();
1797  case 0xf4: // call_p();
1798  case 0xf5: // push_af();
1799  case 0xf6: // or_byte();
1800  case 0xf7: // rst_30();
1801  case 0xf8: // ret_m();
1802  case 0xfa: // jp_m();
1803  case 0xfb: // ei();
1804  case 0xfc: // call_m();
1805  case 0xfe: // cp_byte();
1806  case 0xff: // rst_38();
1807  if (T::isR800()) {
1808  int c = T::CC_DD + nop(); NEXT;
1809  } else {
1810  T::add(T::CC_DD);
1811  #ifdef USE_COMPUTED_GOTO
1812  goto *(opcodeTable[opcodeDD]);
1813  #else
1814  opcodeMain = opcodeDD;
1815  goto switchopcode;
1816  #endif
1817  }
1818 
1819  case 0x09: { int c = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1820  case 0x19: { int c = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1821  case 0x29: { int c = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1822  case 0x39: { int c = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1823  case 0x21: { int c = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1824  case 0x22: { int c = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1825  case 0x2a: { int c = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1826  case 0x23: { int c = inc_SS<IX,T::CC_DD>(); NEXT; }
1827  case 0x2b: { int c = dec_SS<IX,T::CC_DD>(); NEXT; }
1828  case 0x24: { int c = inc_R<IXH,T::CC_DD>(); NEXT; }
1829  case 0x2c: { int c = inc_R<IXL,T::CC_DD>(); NEXT; }
1830  case 0x25: { int c = dec_R<IXH,T::CC_DD>(); NEXT; }
1831  case 0x2d: { int c = dec_R<IXL,T::CC_DD>(); NEXT; }
1832  case 0x26: { int c = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1833  case 0x2e: { int c = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1834  case 0x34: { int c = inc_xix<IX>(); NEXT; }
1835  case 0x35: { int c = dec_xix<IX>(); NEXT; }
1836  case 0x36: { int c = ld_xix_byte<IX>(); NEXT; }
1837 
1838  case 0x44: { int c = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1839  case 0x45: { int c = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1840  case 0x4c: { int c = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1841  case 0x4d: { int c = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1842  case 0x54: { int c = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1843  case 0x55: { int c = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1844  case 0x5c: { int c = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1845  case 0x5d: { int c = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1846  case 0x7c: { int c = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1847  case 0x7d: { int c = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1848  case 0x60: { int c = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1849  case 0x61: { int c = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1850  case 0x62: { int c = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1851  case 0x63: { int c = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1852  case 0x65: { int c = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1853  case 0x67: { int c = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1854  case 0x68: { int c = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1855  case 0x69: { int c = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1856  case 0x6a: { int c = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1857  case 0x6b: { int c = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1858  case 0x6c: { int c = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1859  case 0x6f: { int c = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1860  case 0x70: { int c = ld_xix_R<IX,B>(); NEXT; }
1861  case 0x71: { int c = ld_xix_R<IX,C>(); NEXT; }
1862  case 0x72: { int c = ld_xix_R<IX,D>(); NEXT; }
1863  case 0x73: { int c = ld_xix_R<IX,E>(); NEXT; }
1864  case 0x74: { int c = ld_xix_R<IX,H>(); NEXT; }
1865  case 0x75: { int c = ld_xix_R<IX,L>(); NEXT; }
1866  case 0x77: { int c = ld_xix_R<IX,A>(); NEXT; }
1867  case 0x46: { int c = ld_R_xix<B,IX>(); NEXT; }
1868  case 0x4e: { int c = ld_R_xix<C,IX>(); NEXT; }
1869  case 0x56: { int c = ld_R_xix<D,IX>(); NEXT; }
1870  case 0x5e: { int c = ld_R_xix<E,IX>(); NEXT; }
1871  case 0x66: { int c = ld_R_xix<H,IX>(); NEXT; }
1872  case 0x6e: { int c = ld_R_xix<L,IX>(); NEXT; }
1873  case 0x7e: { int c = ld_R_xix<A,IX>(); NEXT; }
1874 
1875  case 0x84: { int c = add_a_R<IXH,T::CC_DD>(); NEXT; }
1876  case 0x85: { int c = add_a_R<IXL,T::CC_DD>(); NEXT; }
1877  case 0x86: { int c = add_a_xix<IX>(); NEXT; }
1878  case 0x8c: { int c = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1879  case 0x8d: { int c = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1880  case 0x8e: { int c = adc_a_xix<IX>(); NEXT; }
1881  case 0x94: { int c = sub_R<IXH,T::CC_DD>(); NEXT; }
1882  case 0x95: { int c = sub_R<IXL,T::CC_DD>(); NEXT; }
1883  case 0x96: { int c = sub_xix<IX>(); NEXT; }
1884  case 0x9c: { int c = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1885  case 0x9d: { int c = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1886  case 0x9e: { int c = sbc_a_xix<IX>(); NEXT; }
1887  case 0xa4: { int c = and_R<IXH,T::CC_DD>(); NEXT; }
1888  case 0xa5: { int c = and_R<IXL,T::CC_DD>(); NEXT; }
1889  case 0xa6: { int c = and_xix<IX>(); NEXT; }
1890  case 0xac: { int c = xor_R<IXH,T::CC_DD>(); NEXT; }
1891  case 0xad: { int c = xor_R<IXL,T::CC_DD>(); NEXT; }
1892  case 0xae: { int c = xor_xix<IX>(); NEXT; }
1893  case 0xb4: { int c = or_R<IXH,T::CC_DD>(); NEXT; }
1894  case 0xb5: { int c = or_R<IXL,T::CC_DD>(); NEXT; }
1895  case 0xb6: { int c = or_xix<IX>(); NEXT; }
1896  case 0xbc: { int c = cp_R<IXH,T::CC_DD>(); NEXT; }
1897  case 0xbd: { int c = cp_R<IXL,T::CC_DD>(); NEXT; }
1898  case 0xbe: { int c = cp_xix<IX>(); NEXT; }
1899 
1900  case 0xe1: { int c = pop_SS <IX,T::CC_DD>(); NEXT; }
1901  case 0xe5: { int c = push_SS<IX,T::CC_DD>(); NEXT; }
1902  case 0xe3: { int c = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1903  case 0xe9: { int c = jp_SS<IX,T::CC_DD>(); NEXT; }
1904  case 0xf9: { int c = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1905  case 0xcb: ixy = getIX(); goto xx_cb;
1906  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1907  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1908  default: UNREACHABLE; return;
1909  }
1910 }
1911 opFD_2:
1912 CASE(FD) {
1913  byte opcodeFD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1914  incR(1);
1915  switch (opcodeFD) {
1916  case 0x00: // nop();
1917  case 0x01: // ld_bc_word();
1918  case 0x02: // ld_xbc_a();
1919  case 0x03: // inc_bc();
1920  case 0x04: // inc_b();
1921  case 0x05: // dec_b();
1922  case 0x06: // ld_b_byte();
1923  case 0x07: // rlca();
1924  case 0x08: // ex_af_af();
1925  case 0x0a: // ld_a_xbc();
1926  case 0x0b: // dec_bc();
1927  case 0x0c: // inc_c();
1928  case 0x0d: // dec_c();
1929  case 0x0e: // ld_c_byte();
1930  case 0x0f: // rrca();
1931  case 0x10: // djnz();
1932  case 0x11: // ld_de_word();
1933  case 0x12: // ld_xde_a();
1934  case 0x13: // inc_de();
1935  case 0x14: // inc_d();
1936  case 0x15: // dec_d();
1937  case 0x16: // ld_d_byte();
1938  case 0x17: // rla();
1939  case 0x18: // jr();
1940  case 0x1a: // ld_a_xde();
1941  case 0x1b: // dec_de();
1942  case 0x1c: // inc_e();
1943  case 0x1d: // dec_e();
1944  case 0x1e: // ld_e_byte();
1945  case 0x1f: // rra();
1946  case 0x20: // jr_nz();
1947  case 0x27: // daa();
1948  case 0x28: // jr_z();
1949  case 0x2f: // cpl();
1950  case 0x30: // jr_nc();
1951  case 0x31: // ld_sp_word();
1952  case 0x32: // ld_xbyte_a();
1953  case 0x33: // inc_sp();
1954  case 0x37: // scf();
1955  case 0x38: // jr_c();
1956  case 0x3a: // ld_a_xbyte();
1957  case 0x3b: // dec_sp();
1958  case 0x3c: // inc_a();
1959  case 0x3d: // dec_a();
1960  case 0x3e: // ld_a_byte();
1961  case 0x3f: // ccf();
1962 
1963  case 0x40: // ld_b_b();
1964  case 0x41: // ld_b_c();
1965  case 0x42: // ld_b_d();
1966  case 0x43: // ld_b_e();
1967  case 0x47: // ld_b_a();
1968  case 0x48: // ld_c_b();
1969  case 0x49: // ld_c_c();
1970  case 0x4a: // ld_c_d();
1971  case 0x4b: // ld_c_e();
1972  case 0x4f: // ld_c_a();
1973  case 0x50: // ld_d_b();
1974  case 0x51: // ld_d_c();
1975  case 0x52: // ld_d_d();
1976  case 0x53: // ld_d_e();
1977  case 0x57: // ld_d_a();
1978  case 0x58: // ld_e_b();
1979  case 0x59: // ld_e_c();
1980  case 0x5a: // ld_e_d();
1981  case 0x5b: // ld_e_e();
1982  case 0x5f: // ld_e_a();
1983  case 0x64: // ld_ixh_ixh(); == nop
1984  case 0x6d: // ld_ixl_ixl(); == nop
1985  case 0x76: // halt();
1986  case 0x78: // ld_a_b();
1987  case 0x79: // ld_a_c();
1988  case 0x7a: // ld_a_d();
1989  case 0x7b: // ld_a_e();
1990  case 0x7f: // ld_a_a();
1991 
1992  case 0x80: // add_a_b();
1993  case 0x81: // add_a_c();
1994  case 0x82: // add_a_d();
1995  case 0x83: // add_a_e();
1996  case 0x87: // add_a_a();
1997  case 0x88: // adc_a_b();
1998  case 0x89: // adc_a_c();
1999  case 0x8a: // adc_a_d();
2000  case 0x8b: // adc_a_e();
2001  case 0x8f: // adc_a_a();
2002  case 0x90: // sub_b();
2003  case 0x91: // sub_c();
2004  case 0x92: // sub_d();
2005  case 0x93: // sub_e();
2006  case 0x97: // sub_a();
2007  case 0x98: // sbc_a_b();
2008  case 0x99: // sbc_a_c();
2009  case 0x9a: // sbc_a_d();
2010  case 0x9b: // sbc_a_e();
2011  case 0x9f: // sbc_a_a();
2012  case 0xa0: // and_b();
2013  case 0xa1: // and_c();
2014  case 0xa2: // and_d();
2015  case 0xa3: // and_e();
2016  case 0xa7: // and_a();
2017  case 0xa8: // xor_b();
2018  case 0xa9: // xor_c();
2019  case 0xaa: // xor_d();
2020  case 0xab: // xor_e();
2021  case 0xaf: // xor_a();
2022  case 0xb0: // or_b();
2023  case 0xb1: // or_c();
2024  case 0xb2: // or_d();
2025  case 0xb3: // or_e();
2026  case 0xb7: // or_a();
2027  case 0xb8: // cp_b();
2028  case 0xb9: // cp_c();
2029  case 0xba: // cp_d();
2030  case 0xbb: // cp_e();
2031  case 0xbf: // cp_a();
2032 
2033  case 0xc0: // ret_nz();
2034  case 0xc1: // pop_bc();
2035  case 0xc2: // jp_nz();
2036  case 0xc3: // jp();
2037  case 0xc4: // call_nz();
2038  case 0xc5: // push_bc();
2039  case 0xc6: // add_a_byte();
2040  case 0xc7: // rst_00();
2041  case 0xc8: // ret_z();
2042  case 0xc9: // ret();
2043  case 0xca: // jp_z();
2044  case 0xcc: // call_z();
2045  case 0xcd: // call();
2046  case 0xce: // adc_a_byte();
2047  case 0xcf: // rst_08();
2048  case 0xd0: // ret_nc();
2049  case 0xd1: // pop_de();
2050  case 0xd2: // jp_nc();
2051  case 0xd3: // out_byte_a();
2052  case 0xd4: // call_nc();
2053  case 0xd5: // push_de();
2054  case 0xd6: // sub_byte();
2055  case 0xd7: // rst_10();
2056  case 0xd8: // ret_c();
2057  case 0xd9: // exx();
2058  case 0xda: // jp_c();
2059  case 0xdb: // in_a_byte();
2060  case 0xdc: // call_c();
2061  case 0xde: // sbc_a_byte();
2062  case 0xdf: // rst_18();
2063  case 0xe0: // ret_po();
2064  case 0xe2: // jp_po();
2065  case 0xe4: // call_po();
2066  case 0xe6: // and_byte();
2067  case 0xe7: // rst_20();
2068  case 0xe8: // ret_pe();
2069  case 0xea: // jp_pe();
2070  case 0xeb: // ex_de_hl();
2071  case 0xec: // call_pe();
2072  case 0xed: // ed();
2073  case 0xee: // xor_byte();
2074  case 0xef: // rst_28();
2075  case 0xf0: // ret_p();
2076  case 0xf1: // pop_af();
2077  case 0xf2: // jp_p();
2078  case 0xf3: // di();
2079  case 0xf4: // call_p();
2080  case 0xf5: // push_af();
2081  case 0xf6: // or_byte();
2082  case 0xf7: // rst_30();
2083  case 0xf8: // ret_m();
2084  case 0xfa: // jp_m();
2085  case 0xfb: // ei();
2086  case 0xfc: // call_m();
2087  case 0xfe: // cp_byte();
2088  case 0xff: // rst_38();
2089  if (T::isR800()) {
2090  int c = T::CC_DD + nop(); NEXT;
2091  } else {
2092  T::add(T::CC_DD);
2093  #ifdef USE_COMPUTED_GOTO
2094  goto *(opcodeTable[opcodeFD]);
2095  #else
2096  opcodeMain = opcodeFD;
2097  goto switchopcode;
2098  #endif
2099  }
2100 
2101  case 0x09: { int c = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2102  case 0x19: { int c = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2103  case 0x29: { int c = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2104  case 0x39: { int c = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2105  case 0x21: { int c = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2106  case 0x22: { int c = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2107  case 0x2a: { int c = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2108  case 0x23: { int c = inc_SS<IY,T::CC_DD>(); NEXT; }
2109  case 0x2b: { int c = dec_SS<IY,T::CC_DD>(); NEXT; }
2110  case 0x24: { int c = inc_R<IYH,T::CC_DD>(); NEXT; }
2111  case 0x2c: { int c = inc_R<IYL,T::CC_DD>(); NEXT; }
2112  case 0x25: { int c = dec_R<IYH,T::CC_DD>(); NEXT; }
2113  case 0x2d: { int c = dec_R<IYL,T::CC_DD>(); NEXT; }
2114  case 0x26: { int c = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2115  case 0x2e: { int c = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2116  case 0x34: { int c = inc_xix<IY>(); NEXT; }
2117  case 0x35: { int c = dec_xix<IY>(); NEXT; }
2118  case 0x36: { int c = ld_xix_byte<IY>(); NEXT; }
2119 
2120  case 0x44: { int c = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2121  case 0x45: { int c = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2122  case 0x4c: { int c = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2123  case 0x4d: { int c = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2124  case 0x54: { int c = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2125  case 0x55: { int c = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2126  case 0x5c: { int c = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2127  case 0x5d: { int c = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2128  case 0x7c: { int c = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2129  case 0x7d: { int c = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2130  case 0x60: { int c = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2131  case 0x61: { int c = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2132  case 0x62: { int c = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2133  case 0x63: { int c = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2134  case 0x65: { int c = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2135  case 0x67: { int c = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2136  case 0x68: { int c = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2137  case 0x69: { int c = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2138  case 0x6a: { int c = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2139  case 0x6b: { int c = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2140  case 0x6c: { int c = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2141  case 0x6f: { int c = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2142  case 0x70: { int c = ld_xix_R<IY,B>(); NEXT; }
2143  case 0x71: { int c = ld_xix_R<IY,C>(); NEXT; }
2144  case 0x72: { int c = ld_xix_R<IY,D>(); NEXT; }
2145  case 0x73: { int c = ld_xix_R<IY,E>(); NEXT; }
2146  case 0x74: { int c = ld_xix_R<IY,H>(); NEXT; }
2147  case 0x75: { int c = ld_xix_R<IY,L>(); NEXT; }
2148  case 0x77: { int c = ld_xix_R<IY,A>(); NEXT; }
2149  case 0x46: { int c = ld_R_xix<B,IY>(); NEXT; }
2150  case 0x4e: { int c = ld_R_xix<C,IY>(); NEXT; }
2151  case 0x56: { int c = ld_R_xix<D,IY>(); NEXT; }
2152  case 0x5e: { int c = ld_R_xix<E,IY>(); NEXT; }
2153  case 0x66: { int c = ld_R_xix<H,IY>(); NEXT; }
2154  case 0x6e: { int c = ld_R_xix<L,IY>(); NEXT; }
2155  case 0x7e: { int c = ld_R_xix<A,IY>(); NEXT; }
2156 
2157  case 0x84: { int c = add_a_R<IYH,T::CC_DD>(); NEXT; }
2158  case 0x85: { int c = add_a_R<IYL,T::CC_DD>(); NEXT; }
2159  case 0x86: { int c = add_a_xix<IY>(); NEXT; }
2160  case 0x8c: { int c = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2161  case 0x8d: { int c = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2162  case 0x8e: { int c = adc_a_xix<IY>(); NEXT; }
2163  case 0x94: { int c = sub_R<IYH,T::CC_DD>(); NEXT; }
2164  case 0x95: { int c = sub_R<IYL,T::CC_DD>(); NEXT; }
2165  case 0x96: { int c = sub_xix<IY>(); NEXT; }
2166  case 0x9c: { int c = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2167  case 0x9d: { int c = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2168  case 0x9e: { int c = sbc_a_xix<IY>(); NEXT; }
2169  case 0xa4: { int c = and_R<IYH,T::CC_DD>(); NEXT; }
2170  case 0xa5: { int c = and_R<IYL,T::CC_DD>(); NEXT; }
2171  case 0xa6: { int c = and_xix<IY>(); NEXT; }
2172  case 0xac: { int c = xor_R<IYH,T::CC_DD>(); NEXT; }
2173  case 0xad: { int c = xor_R<IYL,T::CC_DD>(); NEXT; }
2174  case 0xae: { int c = xor_xix<IY>(); NEXT; }
2175  case 0xb4: { int c = or_R<IYH,T::CC_DD>(); NEXT; }
2176  case 0xb5: { int c = or_R<IYL,T::CC_DD>(); NEXT; }
2177  case 0xb6: { int c = or_xix<IY>(); NEXT; }
2178  case 0xbc: { int c = cp_R<IYH,T::CC_DD>(); NEXT; }
2179  case 0xbd: { int c = cp_R<IYL,T::CC_DD>(); NEXT; }
2180  case 0xbe: { int c = cp_xix<IY>(); NEXT; }
2181 
2182  case 0xe1: { int c = pop_SS <IY,T::CC_DD>(); NEXT; }
2183  case 0xe5: { int c = push_SS<IY,T::CC_DD>(); NEXT; }
2184  case 0xe3: { int c = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2185  case 0xe9: { int c = jp_SS<IY,T::CC_DD>(); NEXT; }
2186  case 0xf9: { int c = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2187  case 0xcb: ixy = getIY(); goto xx_cb;
2188  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2189  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2190  default: UNREACHABLE; return;
2191  }
2192 }
2193 #ifndef USE_COMPUTED_GOTO
2194  default: UNREACHABLE; return;
2195 }
2196 #endif
2197 
2198 xx_cb: {
2199  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_DD_CB);
2200  offset ofst = tmp & 0xFF;
2201  unsigned addr = (ixy + ofst) & 0xFFFF;
2202  byte xxcb_opcode = tmp >> 8;
2203  switch (xxcb_opcode) {
2204  case 0x00: { int c = rlc_xix_R<B>(addr); NEXT; }
2205  case 0x01: { int c = rlc_xix_R<C>(addr); NEXT; }
2206  case 0x02: { int c = rlc_xix_R<D>(addr); NEXT; }
2207  case 0x03: { int c = rlc_xix_R<E>(addr); NEXT; }
2208  case 0x04: { int c = rlc_xix_R<H>(addr); NEXT; }
2209  case 0x05: { int c = rlc_xix_R<L>(addr); NEXT; }
2210  case 0x06: { int c = rlc_xix_R<DUMMY>(addr); NEXT; }
2211  case 0x07: { int c = rlc_xix_R<A>(addr); NEXT; }
2212  case 0x08: { int c = rrc_xix_R<B>(addr); NEXT; }
2213  case 0x09: { int c = rrc_xix_R<C>(addr); NEXT; }
2214  case 0x0a: { int c = rrc_xix_R<D>(addr); NEXT; }
2215  case 0x0b: { int c = rrc_xix_R<E>(addr); NEXT; }
2216  case 0x0c: { int c = rrc_xix_R<H>(addr); NEXT; }
2217  case 0x0d: { int c = rrc_xix_R<L>(addr); NEXT; }
2218  case 0x0e: { int c = rrc_xix_R<DUMMY>(addr); NEXT; }
2219  case 0x0f: { int c = rrc_xix_R<A>(addr); NEXT; }
2220  case 0x10: { int c = rl_xix_R<B>(addr); NEXT; }
2221  case 0x11: { int c = rl_xix_R<C>(addr); NEXT; }
2222  case 0x12: { int c = rl_xix_R<D>(addr); NEXT; }
2223  case 0x13: { int c = rl_xix_R<E>(addr); NEXT; }
2224  case 0x14: { int c = rl_xix_R<H>(addr); NEXT; }
2225  case 0x15: { int c = rl_xix_R<L>(addr); NEXT; }
2226  case 0x16: { int c = rl_xix_R<DUMMY>(addr); NEXT; }
2227  case 0x17: { int c = rl_xix_R<A>(addr); NEXT; }
2228  case 0x18: { int c = rr_xix_R<B>(addr); NEXT; }
2229  case 0x19: { int c = rr_xix_R<C>(addr); NEXT; }
2230  case 0x1a: { int c = rr_xix_R<D>(addr); NEXT; }
2231  case 0x1b: { int c = rr_xix_R<E>(addr); NEXT; }
2232  case 0x1c: { int c = rr_xix_R<H>(addr); NEXT; }
2233  case 0x1d: { int c = rr_xix_R<L>(addr); NEXT; }
2234  case 0x1e: { int c = rr_xix_R<DUMMY>(addr); NEXT; }
2235  case 0x1f: { int c = rr_xix_R<A>(addr); NEXT; }
2236  case 0x20: { int c = sla_xix_R<B>(addr); NEXT; }
2237  case 0x21: { int c = sla_xix_R<C>(addr); NEXT; }
2238  case 0x22: { int c = sla_xix_R<D>(addr); NEXT; }
2239  case 0x23: { int c = sla_xix_R<E>(addr); NEXT; }
2240  case 0x24: { int c = sla_xix_R<H>(addr); NEXT; }
2241  case 0x25: { int c = sla_xix_R<L>(addr); NEXT; }
2242  case 0x26: { int c = sla_xix_R<DUMMY>(addr); NEXT; }
2243  case 0x27: { int c = sla_xix_R<A>(addr); NEXT; }
2244  case 0x28: { int c = sra_xix_R<B>(addr); NEXT; }
2245  case 0x29: { int c = sra_xix_R<C>(addr); NEXT; }
2246  case 0x2a: { int c = sra_xix_R<D>(addr); NEXT; }
2247  case 0x2b: { int c = sra_xix_R<E>(addr); NEXT; }
2248  case 0x2c: { int c = sra_xix_R<H>(addr); NEXT; }
2249  case 0x2d: { int c = sra_xix_R<L>(addr); NEXT; }
2250  case 0x2e: { int c = sra_xix_R<DUMMY>(addr); NEXT; }
2251  case 0x2f: { int c = sra_xix_R<A>(addr); NEXT; }
2252  case 0x30: { int c = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2253  case 0x31: { int c = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2254  case 0x32: { int c = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2255  case 0x33: { int c = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2256  case 0x34: { int c = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2257  case 0x35: { int c = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2258  case 0x36: { int c = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2259  case 0x37: { int c = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2260  case 0x38: { int c = srl_xix_R<B>(addr); NEXT; }
2261  case 0x39: { int c = srl_xix_R<C>(addr); NEXT; }
2262  case 0x3a: { int c = srl_xix_R<D>(addr); NEXT; }
2263  case 0x3b: { int c = srl_xix_R<E>(addr); NEXT; }
2264  case 0x3c: { int c = srl_xix_R<H>(addr); NEXT; }
2265  case 0x3d: { int c = srl_xix_R<L>(addr); NEXT; }
2266  case 0x3e: { int c = srl_xix_R<DUMMY>(addr); NEXT; }
2267  case 0x3f: { int c = srl_xix_R<A>(addr); NEXT; }
2268 
2269  case 0x40: case 0x41: case 0x42: case 0x43:
2270  case 0x44: case 0x45: case 0x46: case 0x47:
2271  { int c = bit_N_xix<0>(addr); NEXT; }
2272  case 0x48: case 0x49: case 0x4a: case 0x4b:
2273  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2274  { int c = bit_N_xix<1>(addr); NEXT; }
2275  case 0x50: case 0x51: case 0x52: case 0x53:
2276  case 0x54: case 0x55: case 0x56: case 0x57:
2277  { int c = bit_N_xix<2>(addr); NEXT; }
2278  case 0x58: case 0x59: case 0x5a: case 0x5b:
2279  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2280  { int c = bit_N_xix<3>(addr); NEXT; }
2281  case 0x60: case 0x61: case 0x62: case 0x63:
2282  case 0x64: case 0x65: case 0x66: case 0x67:
2283  { int c = bit_N_xix<4>(addr); NEXT; }
2284  case 0x68: case 0x69: case 0x6a: case 0x6b:
2285  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2286  { int c = bit_N_xix<5>(addr); NEXT; }
2287  case 0x70: case 0x71: case 0x72: case 0x73:
2288  case 0x74: case 0x75: case 0x76: case 0x77:
2289  { int c = bit_N_xix<6>(addr); NEXT; }
2290  case 0x78: case 0x79: case 0x7a: case 0x7b:
2291  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2292  { int c = bit_N_xix<7>(addr); NEXT; }
2293 
2294  case 0x80: { int c = res_N_xix_R<0,B>(addr); NEXT; }
2295  case 0x81: { int c = res_N_xix_R<0,C>(addr); NEXT; }
2296  case 0x82: { int c = res_N_xix_R<0,D>(addr); NEXT; }
2297  case 0x83: { int c = res_N_xix_R<0,E>(addr); NEXT; }
2298  case 0x84: { int c = res_N_xix_R<0,H>(addr); NEXT; }
2299  case 0x85: { int c = res_N_xix_R<0,L>(addr); NEXT; }
2300  case 0x87: { int c = res_N_xix_R<0,A>(addr); NEXT; }
2301  case 0x88: { int c = res_N_xix_R<1,B>(addr); NEXT; }
2302  case 0x89: { int c = res_N_xix_R<1,C>(addr); NEXT; }
2303  case 0x8a: { int c = res_N_xix_R<1,D>(addr); NEXT; }
2304  case 0x8b: { int c = res_N_xix_R<1,E>(addr); NEXT; }
2305  case 0x8c: { int c = res_N_xix_R<1,H>(addr); NEXT; }
2306  case 0x8d: { int c = res_N_xix_R<1,L>(addr); NEXT; }
2307  case 0x8f: { int c = res_N_xix_R<1,A>(addr); NEXT; }
2308  case 0x90: { int c = res_N_xix_R<2,B>(addr); NEXT; }
2309  case 0x91: { int c = res_N_xix_R<2,C>(addr); NEXT; }
2310  case 0x92: { int c = res_N_xix_R<2,D>(addr); NEXT; }
2311  case 0x93: { int c = res_N_xix_R<2,E>(addr); NEXT; }
2312  case 0x94: { int c = res_N_xix_R<2,H>(addr); NEXT; }
2313  case 0x95: { int c = res_N_xix_R<2,L>(addr); NEXT; }
2314  case 0x97: { int c = res_N_xix_R<2,A>(addr); NEXT; }
2315  case 0x98: { int c = res_N_xix_R<3,B>(addr); NEXT; }
2316  case 0x99: { int c = res_N_xix_R<3,C>(addr); NEXT; }
2317  case 0x9a: { int c = res_N_xix_R<3,D>(addr); NEXT; }
2318  case 0x9b: { int c = res_N_xix_R<3,E>(addr); NEXT; }
2319  case 0x9c: { int c = res_N_xix_R<3,H>(addr); NEXT; }
2320  case 0x9d: { int c = res_N_xix_R<3,L>(addr); NEXT; }
2321  case 0x9f: { int c = res_N_xix_R<3,A>(addr); NEXT; }
2322  case 0xa0: { int c = res_N_xix_R<4,B>(addr); NEXT; }
2323  case 0xa1: { int c = res_N_xix_R<4,C>(addr); NEXT; }
2324  case 0xa2: { int c = res_N_xix_R<4,D>(addr); NEXT; }
2325  case 0xa3: { int c = res_N_xix_R<4,E>(addr); NEXT; }
2326  case 0xa4: { int c = res_N_xix_R<4,H>(addr); NEXT; }
2327  case 0xa5: { int c = res_N_xix_R<4,L>(addr); NEXT; }
2328  case 0xa7: { int c = res_N_xix_R<4,A>(addr); NEXT; }
2329  case 0xa8: { int c = res_N_xix_R<5,B>(addr); NEXT; }
2330  case 0xa9: { int c = res_N_xix_R<5,C>(addr); NEXT; }
2331  case 0xaa: { int c = res_N_xix_R<5,D>(addr); NEXT; }
2332  case 0xab: { int c = res_N_xix_R<5,E>(addr); NEXT; }
2333  case 0xac: { int c = res_N_xix_R<5,H>(addr); NEXT; }
2334  case 0xad: { int c = res_N_xix_R<5,L>(addr); NEXT; }
2335  case 0xaf: { int c = res_N_xix_R<5,A>(addr); NEXT; }
2336  case 0xb0: { int c = res_N_xix_R<6,B>(addr); NEXT; }
2337  case 0xb1: { int c = res_N_xix_R<6,C>(addr); NEXT; }
2338  case 0xb2: { int c = res_N_xix_R<6,D>(addr); NEXT; }
2339  case 0xb3: { int c = res_N_xix_R<6,E>(addr); NEXT; }
2340  case 0xb4: { int c = res_N_xix_R<6,H>(addr); NEXT; }
2341  case 0xb5: { int c = res_N_xix_R<6,L>(addr); NEXT; }
2342  case 0xb7: { int c = res_N_xix_R<6,A>(addr); NEXT; }
2343  case 0xb8: { int c = res_N_xix_R<7,B>(addr); NEXT; }
2344  case 0xb9: { int c = res_N_xix_R<7,C>(addr); NEXT; }
2345  case 0xba: { int c = res_N_xix_R<7,D>(addr); NEXT; }
2346  case 0xbb: { int c = res_N_xix_R<7,E>(addr); NEXT; }
2347  case 0xbc: { int c = res_N_xix_R<7,H>(addr); NEXT; }
2348  case 0xbd: { int c = res_N_xix_R<7,L>(addr); NEXT; }
2349  case 0xbf: { int c = res_N_xix_R<7,A>(addr); NEXT; }
2350  case 0x86: { int c = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2351  case 0x8e: { int c = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2352  case 0x96: { int c = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2353  case 0x9e: { int c = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2354  case 0xa6: { int c = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2355  case 0xae: { int c = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2356  case 0xb6: { int c = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2357  case 0xbe: { int c = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2358 
2359  case 0xc0: { int c = set_N_xix_R<0,B>(addr); NEXT; }
2360  case 0xc1: { int c = set_N_xix_R<0,C>(addr); NEXT; }
2361  case 0xc2: { int c = set_N_xix_R<0,D>(addr); NEXT; }
2362  case 0xc3: { int c = set_N_xix_R<0,E>(addr); NEXT; }
2363  case 0xc4: { int c = set_N_xix_R<0,H>(addr); NEXT; }
2364  case 0xc5: { int c = set_N_xix_R<0,L>(addr); NEXT; }
2365  case 0xc7: { int c = set_N_xix_R<0,A>(addr); NEXT; }
2366  case 0xc8: { int c = set_N_xix_R<1,B>(addr); NEXT; }
2367  case 0xc9: { int c = set_N_xix_R<1,C>(addr); NEXT; }
2368  case 0xca: { int c = set_N_xix_R<1,D>(addr); NEXT; }
2369  case 0xcb: { int c = set_N_xix_R<1,E>(addr); NEXT; }
2370  case 0xcc: { int c = set_N_xix_R<1,H>(addr); NEXT; }
2371  case 0xcd: { int c = set_N_xix_R<1,L>(addr); NEXT; }
2372  case 0xcf: { int c = set_N_xix_R<1,A>(addr); NEXT; }
2373  case 0xd0: { int c = set_N_xix_R<2,B>(addr); NEXT; }
2374  case 0xd1: { int c = set_N_xix_R<2,C>(addr); NEXT; }
2375  case 0xd2: { int c = set_N_xix_R<2,D>(addr); NEXT; }
2376  case 0xd3: { int c = set_N_xix_R<2,E>(addr); NEXT; }
2377  case 0xd4: { int c = set_N_xix_R<2,H>(addr); NEXT; }
2378  case 0xd5: { int c = set_N_xix_R<2,L>(addr); NEXT; }
2379  case 0xd7: { int c = set_N_xix_R<2,A>(addr); NEXT; }
2380  case 0xd8: { int c = set_N_xix_R<3,B>(addr); NEXT; }
2381  case 0xd9: { int c = set_N_xix_R<3,C>(addr); NEXT; }
2382  case 0xda: { int c = set_N_xix_R<3,D>(addr); NEXT; }
2383  case 0xdb: { int c = set_N_xix_R<3,E>(addr); NEXT; }
2384  case 0xdc: { int c = set_N_xix_R<3,H>(addr); NEXT; }
2385  case 0xdd: { int c = set_N_xix_R<3,L>(addr); NEXT; }
2386  case 0xdf: { int c = set_N_xix_R<3,A>(addr); NEXT; }
2387  case 0xe0: { int c = set_N_xix_R<4,B>(addr); NEXT; }
2388  case 0xe1: { int c = set_N_xix_R<4,C>(addr); NEXT; }
2389  case 0xe2: { int c = set_N_xix_R<4,D>(addr); NEXT; }
2390  case 0xe3: { int c = set_N_xix_R<4,E>(addr); NEXT; }
2391  case 0xe4: { int c = set_N_xix_R<4,H>(addr); NEXT; }
2392  case 0xe5: { int c = set_N_xix_R<4,L>(addr); NEXT; }
2393  case 0xe7: { int c = set_N_xix_R<4,A>(addr); NEXT; }
2394  case 0xe8: { int c = set_N_xix_R<5,B>(addr); NEXT; }
2395  case 0xe9: { int c = set_N_xix_R<5,C>(addr); NEXT; }
2396  case 0xea: { int c = set_N_xix_R<5,D>(addr); NEXT; }
2397  case 0xeb: { int c = set_N_xix_R<5,E>(addr); NEXT; }
2398  case 0xec: { int c = set_N_xix_R<5,H>(addr); NEXT; }
2399  case 0xed: { int c = set_N_xix_R<5,L>(addr); NEXT; }
2400  case 0xef: { int c = set_N_xix_R<5,A>(addr); NEXT; }
2401  case 0xf0: { int c = set_N_xix_R<6,B>(addr); NEXT; }
2402  case 0xf1: { int c = set_N_xix_R<6,C>(addr); NEXT; }
2403  case 0xf2: { int c = set_N_xix_R<6,D>(addr); NEXT; }
2404  case 0xf3: { int c = set_N_xix_R<6,E>(addr); NEXT; }
2405  case 0xf4: { int c = set_N_xix_R<6,H>(addr); NEXT; }
2406  case 0xf5: { int c = set_N_xix_R<6,L>(addr); NEXT; }
2407  case 0xf7: { int c = set_N_xix_R<6,A>(addr); NEXT; }
2408  case 0xf8: { int c = set_N_xix_R<7,B>(addr); NEXT; }
2409  case 0xf9: { int c = set_N_xix_R<7,C>(addr); NEXT; }
2410  case 0xfa: { int c = set_N_xix_R<7,D>(addr); NEXT; }
2411  case 0xfb: { int c = set_N_xix_R<7,E>(addr); NEXT; }
2412  case 0xfc: { int c = set_N_xix_R<7,H>(addr); NEXT; }
2413  case 0xfd: { int c = set_N_xix_R<7,L>(addr); NEXT; }
2414  case 0xff: { int c = set_N_xix_R<7,A>(addr); NEXT; }
2415  case 0xc6: { int c = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2416  case 0xce: { int c = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2417  case 0xd6: { int c = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2418  case 0xde: { int c = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2419  case 0xe6: { int c = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2420  case 0xee: { int c = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2421  case 0xf6: { int c = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2422  case 0xfe: { int c = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2423  default: UNREACHABLE;
2424  }
2425  }
2426 }
2427 
2428 template<class T> inline void CPUCore<T>::cpuTracePre()
2429 {
2430  start_pc = getPC();
2431 }
2432 template<class T> inline void CPUCore<T>::cpuTracePost()
2433 {
2434  if (unlikely(tracingEnabled)) {
2435  cpuTracePost_slow();
2436  }
2437 }
2438 template<class T> void CPUCore<T>::cpuTracePost_slow()
2439 {
2440  byte opbuf[4];
2441  string dasmOutput;
2442  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2443  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2444  << " : " << dasmOutput
2445  << " AF=" << std::setw(4) << getAF()
2446  << " BC=" << std::setw(4) << getBC()
2447  << " DE=" << std::setw(4) << getDE()
2448  << " HL=" << std::setw(4) << getHL()
2449  << " IX=" << std::setw(4) << getIX()
2450  << " IY=" << std::setw(4) << getIY()
2451  << " SP=" << std::setw(4) << getSP()
2452  << std::endl << std::dec;
2453 }
2454 
2455 template<class T> void CPUCore<T>::executeSlow()
2456 {
2457  if (unlikely(false && nmiEdge)) {
2458  // Note: NMIs are disabled, see also raiseNMI()
2459  nmiEdge = false;
2460  nmi(); // NMI occured
2461  } else if (unlikely(IRQStatus && getIFF1() && !getAfterEI())) {
2462  // normal interrupt
2463  if (unlikely(getAfterLDAI())) {
2464  // HACK!!!
2465  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2466  // bit to the V flag. Though when the Z80 accepts an
2467  // IRQ directly after this instruction, the V flag is 0
2468  // (instead of the expected value 1). This can probably
2469  // be explained if you look at the pipeline of the Z80.
2470  // But for speed reasons we implement it here as a
2471  // fix-up (a hack) in the IRQ routine. This behaviour
2472  // is actually a bug in the Z80.
2473  // Thanks to n_n for reporting this behaviour. I think
2474  // this was discovered by GuyveR800. Also thanks to
2475  // n_n for writing a test program that demonstrates
2476  // this quirk.
2477  // I also wrote a test program that demonstrates this
2478  // behaviour is the same whether 'ld a,i' is preceded
2479  // by a 'ei' instruction or not (so it's not caused by
2480  // the 'delayed IRQ acceptance of ei').
2481  assert(getF() & V_FLAG);
2482  setF(getF() & ~V_FLAG);
2483  }
2484  IRQAccept.signal();
2485  switch (getIM()) {
2486  case 0: irq0();
2487  break;
2488  case 1: irq1();
2489  break;
2490  case 2: irq2();
2491  break;
2492  default:
2493  UNREACHABLE;
2494  }
2495  } else if (unlikely(getHALT())) {
2496  // in halt mode
2497  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2498  setSlowInstructions();
2499  } else {
2500  assert(isSameAfter());
2501  clearNextAfter();
2502  cpuTracePre();
2503  assert(T::limitReached()); // we want only one instruction
2504  executeInstructions();
2505  cpuTracePost();
2506  copyNextAfter();
2507  }
2508 }
2509 
2510 template<class T> void CPUCore<T>::execute(bool fastForward)
2511 {
2512  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2513  // won't trigger. It is possible we already are in break mode, but
2514  // break is ignored in fast-forward mode.
2515  assert(fastForward || !interface->isBreaked());
2516  if (fastForward) {
2517  interface->setFastForward(true);
2518  }
2519  execute2(fastForward);
2520  interface->setFastForward(false);
2521 }
2522 
2523 template<class T> void CPUCore<T>::execute2(bool fastForward)
2524 {
2525  // note: Don't use getTimeFast() here, because 'once in a while' we
2526  // need to CPUClock::sync() to avoid overflow.
2527  // Should be done at least once per second (approx). So only
2528  // once in this method is enough.
2529  scheduler.schedule(T::getTime());
2530  setSlowInstructions();
2531 
2532  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2533  // at least one instruction
2534  interface->setContinue(false);
2535  executeSlow();
2536  scheduler.schedule(T::getTimeFast());
2537  --slowInstructions;
2538  if (interface->isStep()) {
2539  interface->setStep(false);
2540  interface->doBreak();
2541  return;
2542  }
2543  }
2544 
2545  // Note: we call scheduler _after_ executing the instruction and before
2546  // deciding between executeFast() and executeSlow() (because a
2547  // SyncPoint could set an IRQ and then we must choose executeSlow())
2548  if (fastForward ||
2549  (!interface->anyBreakPoints() && !tracingEnabled)) {
2550  // fast path, no breakpoints, no tracing
2551  while (!needExitCPULoop()) {
2552  if (slowInstructions) {
2553  --slowInstructions;
2554  executeSlow();
2555  scheduler.schedule(T::getTimeFast());
2556  } else {
2557  while (slowInstructions == 0) {
2558  T::enableLimit(); // does CPUClock::sync()
2559  if (likely(!T::limitReached())) {
2560  // multiple instructions
2561  assert(isSameAfter());
2562  executeInstructions();
2563  assert(isSameAfter());
2564  }
2565  scheduler.schedule(T::getTimeFast());
2566  if (needExitCPULoop()) return;
2567  }
2568  }
2569  }
2570  } else {
2571  while (!needExitCPULoop()) {
2572  if (interface->checkBreakPoints(getPC())) {
2573  assert(interface->isBreaked());
2574  break;
2575  }
2576  if (slowInstructions == 0) {
2577  cpuTracePre();
2578  assert(T::limitReached()); // only one instruction
2579  assert(isSameAfter());
2580  executeInstructions();
2581  assert(isSameAfter());
2582  cpuTracePost();
2583  } else {
2584  --slowInstructions;
2585  executeSlow();
2586  }
2587  // Don't use getTimeFast() here, we need a call to
2588  // CPUClock::sync() 'once in a while'. (During a
2589  // reverse fast-forward this wasn't always the case).
2590  scheduler.schedule(T::getTime());
2591  }
2592  }
2593 }
2594 
2595 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2596  if (R8 == A) { return getA(); }
2597  else if (R8 == F) { return getF(); }
2598  else if (R8 == B) { return getB(); }
2599  else if (R8 == C) { return getC(); }
2600  else if (R8 == D) { return getD(); }
2601  else if (R8 == E) { return getE(); }
2602  else if (R8 == H) { return getH(); }
2603  else if (R8 == L) { return getL(); }
2604  else if (R8 == IXH) { return getIXh(); }
2605  else if (R8 == IXL) { return getIXl(); }
2606  else if (R8 == IYH) { return getIYh(); }
2607  else if (R8 == IYL) { return getIYl(); }
2608  else if (R8 == REG_I) { return getI(); }
2609  else if (R8 == REG_R) { return getR(); }
2610  else if (R8 == DUMMY) { return 0; }
2611  else { UNREACHABLE; return 0; }
2612 }
2613 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2614  if (R16 == AF) { return getAF(); }
2615  else if (R16 == BC) { return getBC(); }
2616  else if (R16 == DE) { return getDE(); }
2617  else if (R16 == HL) { return getHL(); }
2618  else if (R16 == IX) { return getIX(); }
2619  else if (R16 == IY) { return getIY(); }
2620  else if (R16 == SP) { return getSP(); }
2621  else { UNREACHABLE; return 0; }
2622 }
2623 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2624  if (R8 == A) { setA(x); }
2625  else if (R8 == F) { setF(x); }
2626  else if (R8 == B) { setB(x); }
2627  else if (R8 == C) { setC(x); }
2628  else if (R8 == D) { setD(x); }
2629  else if (R8 == E) { setE(x); }
2630  else if (R8 == H) { setH(x); }
2631  else if (R8 == L) { setL(x); }
2632  else if (R8 == IXH) { setIXh(x); }
2633  else if (R8 == IXL) { setIXl(x); }
2634  else if (R8 == IYH) { setIYh(x); }
2635  else if (R8 == IYL) { setIYl(x); }
2636  else if (R8 == REG_I) { setI(x); }
2637  else if (R8 == REG_R) { setR(x); }
2638  else if (R8 == DUMMY) { /* nothing */ }
2639  else { UNREACHABLE; }
2640 }
2641 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2642  if (R16 == AF) { setAF(x); }
2643  else if (R16 == BC) { setBC(x); }
2644  else if (R16 == DE) { setDE(x); }
2645  else if (R16 == HL) { setHL(x); }
2646  else if (R16 == IX) { setIX(x); }
2647  else if (R16 == IY) { setIY(x); }
2648  else if (R16 == SP) { setSP(x); }
2649  else { UNREACHABLE; }
2650 }
2651 
2652 // LD r,r
2653 template<class T> template<Reg8 DST, Reg8 SRC, int EE> int CPUCore<T>::ld_R_R() {
2654  set8<DST>(get8<SRC>()); return T::CC_LD_R_R + EE;
2655 }
2656 
2657 // LD SP,ss
2658 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_sp_SS() {
2659  setSP(get16<REG>()); return T::CC_LD_SP_HL + EE;
2660 }
2661 
2662 // LD (ss),a
2663 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_a() {
2664  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2665  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2666  return T::CC_LD_SS_A;
2667 }
2668 
2669 // LD (HL),r
2670 template<class T> template<Reg8 SRC> int CPUCore<T>::ld_xhl_R() {
2671  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2672  return T::CC_LD_HL_R;
2673 }
2674 
2675 // LD (IXY+e),r
2676 template<class T> template<Reg16 IXY, Reg8 SRC> int CPUCore<T>::ld_xix_R() {
2677  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_XIX_R_1);
2678  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2679  T::setMemPtr(addr);
2680  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2681  return T::CC_DD + T::CC_LD_XIX_R;
2682 }
2683 
2684 // LD (HL),n
2685 template<class T> int CPUCore<T>::ld_xhl_byte() {
2686  byte val = RDMEM_OPCODE(T::CC_LD_HL_N_1);
2687  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2688  return T::CC_LD_HL_N;
2689 }
2690 
2691 // LD (IXY+e),n
2692 template<class T> template<Reg16 IXY> int CPUCore<T>::ld_xix_byte() {
2693  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_LD_XIX_N_1);
2694  offset ofst = tmp & 0xFF;
2695  byte val = tmp >> 8;
2696  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2697  T::setMemPtr(addr);
2698  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2699  return T::CC_DD + T::CC_LD_XIX_N;
2700 }
2701 
2702 // LD (nn),A
2703 template<class T> int CPUCore<T>::ld_xbyte_a() {
2704  unsigned x = RD_WORD_PC(T::CC_LD_NN_A_1);
2705  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2706  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2707  return T::CC_LD_NN_A;
2708 }
2709 
2710 // LD (nn),ss
2711 template<class T> template<int EE> inline int CPUCore<T>::WR_NN_Y(unsigned reg) {
2712  unsigned addr = RD_WORD_PC(T::CC_LD_XX_HL_1 + EE);
2713  T::setMemPtr(addr + 1);
2714  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2715  return T::CC_LD_XX_HL + EE;
2716 }
2717 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_xword_SS() {
2718  return WR_NN_Y<EE >(get16<REG>());
2719 }
2720 template<class T> template<Reg16 REG> int CPUCore<T>::ld_xword_SS_ED() {
2721  return WR_NN_Y<T::EE_ED>(get16<REG>());
2722 }
2723 
2724 // LD A,(ss)
2725 template<class T> template<Reg16 REG> int CPUCore<T>::ld_a_SS() {
2726  T::setMemPtr(get16<REG>() + 1);
2727  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2728  return T::CC_LD_A_SS;
2729 }
2730 
2731 // LD A,(nn)
2732 template<class T> int CPUCore<T>::ld_a_xbyte() {
2733  unsigned addr = RD_WORD_PC(T::CC_LD_A_NN_1);
2734  T::setMemPtr(addr + 1);
2735  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2736  return T::CC_LD_A_NN;
2737 }
2738 
2739 // LD r,n
2740 template<class T> template<Reg8 DST, int EE> int CPUCore<T>::ld_R_byte() {
2741  set8<DST>(RDMEM_OPCODE(T::CC_LD_R_N_1 + EE)); return T::CC_LD_R_N + EE;
2742 }
2743 
2744 // LD r,(hl)
2745 template<class T> template<Reg8 DST> int CPUCore<T>::ld_R_xhl() {
2746  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return T::CC_LD_R_HL;
2747 }
2748 
2749 // LD r,(IXY+e)
2750 template<class T> template<Reg8 DST, Reg16 IXY> int CPUCore<T>::ld_R_xix() {
2751  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_R_XIX_1);
2752  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2753  T::setMemPtr(addr);
2754  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2755  return T::CC_DD + T::CC_LD_R_XIX;
2756 }
2757 
2758 // LD ss,(nn)
2759 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2760  unsigned addr = RD_WORD_PC(T::CC_LD_HL_XX_1 + EE);
2761  T::setMemPtr(addr + 1);
2762  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2763  return result;
2764 }
2765 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_xword() {
2766  set16<REG>(RD_P_XX<EE>()); return T::CC_LD_HL_XX + EE;
2767 }
2768 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_xword_ED() {
2769  set16<REG>(RD_P_XX<T::EE_ED>()); return T::CC_LD_HL_XX + T::EE_ED;
2770 }
2771 
2772 // LD ss,nn
2773 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_word() {
2774  set16<REG>(RD_WORD_PC(T::CC_LD_SS_NN_1 + EE)); return T::CC_LD_SS_NN + EE;
2775 }
2776 
2777 
2778 // ADC A,r
2779 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2780  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2781  byte f = ((res & 0x100) ? C_FLAG : 0) |
2782  ((getA() ^ res ^ reg) & H_FLAG) |
2783  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2784  0; // N_FLAG
2785  if (T::isR800()) {
2786  f |= ZSTable[res & 0xFF];
2787  f |= getF() & (X_FLAG | Y_FLAG);
2788  } else {
2789  f |= ZSXYTable[res & 0xFF];
2790  }
2791  setF(f);
2792  setA(res);
2793 }
2794 template<class T> inline int CPUCore<T>::adc_a_a() {
2795  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2796  byte f = ((res & 0x100) ? C_FLAG : 0) |
2797  (res & H_FLAG) |
2798  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2799  0; // N_FLAG
2800  if (T::isR800()) {
2801  f |= ZSTable[res & 0xFF];
2802  f |= getF() & (X_FLAG | Y_FLAG);
2803  } else {
2804  f |= ZSXYTable[res & 0xFF];
2805  }
2806  setF(f);
2807  setA(res);
2808  return T::CC_CP_R;
2809 }
2810 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::adc_a_R() {
2811  ADC(get8<SRC>()); return T::CC_CP_R + EE;
2812 }
2813 template<class T> int CPUCore<T>::adc_a_byte() {
2814  ADC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2815 }
2816 template<class T> int CPUCore<T>::adc_a_xhl() {
2817  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2818 }
2819 template<class T> template<Reg16 IXY> int CPUCore<T>::adc_a_xix() {
2820  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2821  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2822  T::setMemPtr(addr);
2823  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2824  return T::CC_DD + T::CC_CP_XIX;
2825 }
2826 
2827 // ADD A,r
2828 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2829  unsigned res = getA() + reg;
2830  byte f = ((res & 0x100) ? C_FLAG : 0) |
2831  ((getA() ^ res ^ reg) & H_FLAG) |
2832  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2833  0; // N_FLAG
2834  if (T::isR800()) {
2835  f |= ZSTable[res & 0xFF];
2836  f |= getF() & (X_FLAG | Y_FLAG);
2837  } else {
2838  f |= ZSXYTable[res & 0xFF];
2839  }
2840  setF(f);
2841  setA(res);
2842 }
2843 template<class T> inline int CPUCore<T>::add_a_a() {
2844  unsigned res = 2 * getA();
2845  byte f = ((res & 0x100) ? C_FLAG : 0) |
2846  (res & H_FLAG) |
2847  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2848  0; // N_FLAG
2849  if (T::isR800()) {
2850  f |= ZSTable[res & 0xFF];
2851  f |= getF() & (X_FLAG | Y_FLAG);
2852  } else {
2853  f |= ZSXYTable[res & 0xFF];
2854  }
2855  setF(f);
2856  setA(res);
2857  return T::CC_CP_R;
2858 }
2859 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::add_a_R() {
2860  ADD(get8<SRC>()); return T::CC_CP_R + EE;
2861 }
2862 template<class T> int CPUCore<T>::add_a_byte() {
2863  ADD(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2864 }
2865 template<class T> int CPUCore<T>::add_a_xhl() {
2866  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2867 }
2868 template<class T> template<Reg16 IXY> int CPUCore<T>::add_a_xix() {
2869  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2870  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2871  T::setMemPtr(addr);
2872  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2873  return T::CC_DD + T::CC_CP_XIX;
2874 }
2875 
2876 // AND r
2877 template<class T> inline void CPUCore<T>::AND(byte reg) {
2878  setA(getA() & reg);
2879  byte f = 0;
2880  if (T::isR800()) {
2881  f |= ZSPHTable[getA()];
2882  f |= getF() & (X_FLAG | Y_FLAG);
2883  } else {
2884  f |= ZSPXYTable[getA()] | H_FLAG;
2885  }
2886  setF(f);
2887 }
2888 template<class T> int CPUCore<T>::and_a() {
2889  byte f = 0;
2890  if (T::isR800()) {
2891  f |= ZSPHTable[getA()];
2892  f |= getF() & (X_FLAG | Y_FLAG);
2893  } else {
2894  f |= ZSPXYTable[getA()] | H_FLAG;
2895  }
2896  setF(f);
2897  return T::CC_CP_R;
2898 }
2899 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::and_R() {
2900  AND(get8<SRC>()); return T::CC_CP_R + EE;
2901 }
2902 template<class T> int CPUCore<T>::and_byte() {
2903  AND(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2904 }
2905 template<class T> int CPUCore<T>::and_xhl() {
2906  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2907 }
2908 template<class T> template<Reg16 IXY> int CPUCore<T>::and_xix() {
2909  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2910  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2911  T::setMemPtr(addr);
2912  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2913  return T::CC_DD + T::CC_CP_XIX;
2914 }
2915 
2916 // CP r
2917 template<class T> inline void CPUCore<T>::CP(byte reg) {
2918  unsigned q = getA() - reg;
2919  byte f = ZSTable[q & 0xFF] |
2920  ((q & 0x100) ? C_FLAG : 0) |
2921  N_FLAG |
2922  ((getA() ^ q ^ reg) & H_FLAG) |
2923  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2924  if (T::isR800()) {
2925  f |= getF() & (X_FLAG | Y_FLAG);
2926  } else {
2927  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2928  }
2929  setF(f);
2930 }
2931 template<class T> int CPUCore<T>::cp_a() {
2932  byte f = ZS0 | N_FLAG;
2933  if (T::isR800()) {
2934  f |= getF() & (X_FLAG | Y_FLAG);
2935  } else {
2936  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2937  }
2938  setF(f);
2939  return T::CC_CP_R;
2940 }
2941 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::cp_R() {
2942  CP(get8<SRC>()); return T::CC_CP_R + EE;
2943 }
2944 template<class T> int CPUCore<T>::cp_byte() {
2945  CP(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2946 }
2947 template<class T> int CPUCore<T>::cp_xhl() {
2948  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2949 }
2950 template<class T> template<Reg16 IXY> int CPUCore<T>::cp_xix() {
2951  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2952  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2953  T::setMemPtr(addr);
2954  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2955  return T::CC_DD + T::CC_CP_XIX;
2956 }
2957 
2958 // OR r
2959 template<class T> inline void CPUCore<T>::OR(byte reg) {
2960  setA(getA() | reg);
2961  byte f = 0;
2962  if (T::isR800()) {
2963  f |= ZSPTable[getA()];
2964  f |= getF() & (X_FLAG | Y_FLAG);
2965  } else {
2966  f |= ZSPXYTable[getA()];
2967  }
2968  setF(f);
2969 }
2970 template<class T> int CPUCore<T>::or_a() {
2971  byte f = 0;
2972  if (T::isR800()) {
2973  f |= ZSPTable[getA()];
2974  f |= getF() & (X_FLAG | Y_FLAG);
2975  } else {
2976  f |= ZSPXYTable[getA()];
2977  }
2978  setF(f);
2979  return T::CC_CP_R;
2980 }
2981 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::or_R() {
2982  OR(get8<SRC>()); return T::CC_CP_R + EE;
2983 }
2984 template<class T> int CPUCore<T>::or_byte() {
2985  OR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2986 }
2987 template<class T> int CPUCore<T>::or_xhl() {
2988  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2989 }
2990 template<class T> template<Reg16 IXY> int CPUCore<T>::or_xix() {
2991  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2992  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2993  T::setMemPtr(addr);
2994  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2995  return T::CC_DD + T::CC_CP_XIX;
2996 }
2997 
2998 // SBC A,r
2999 template<class T> inline void CPUCore<T>::SBC(byte reg) {
3000  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
3001  byte f = ((res & 0x100) ? C_FLAG : 0) |
3002  N_FLAG |
3003  ((getA() ^ res ^ reg) & H_FLAG) |
3004  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3005  if (T::isR800()) {
3006  f |= ZSTable[res & 0xFF];
3007  f |= getF() & (X_FLAG | Y_FLAG);
3008  } else {
3009  f |= ZSXYTable[res & 0xFF];
3010  }
3011  setF(f);
3012  setA(res);
3013 }
3014 template<class T> int CPUCore<T>::sbc_a_a() {
3015  if (T::isR800()) {
3016  word t = (getF() & C_FLAG)
3017  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3018  : ( 0 * 256 | ZS0 | N_FLAG);
3019  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3020  } else {
3021  setAF((getF() & C_FLAG) ?
3022  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3023  ( 0 * 256 | ZSXY0 | N_FLAG));
3024  }
3025  return T::CC_CP_R;
3026 }
3027 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sbc_a_R() {
3028  SBC(get8<SRC>()); return T::CC_CP_R + EE;
3029 }
3030 template<class T> int CPUCore<T>::sbc_a_byte() {
3031  SBC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3032 }
3033 template<class T> int CPUCore<T>::sbc_a_xhl() {
3034  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3035 }
3036 template<class T> template<Reg16 IXY> int CPUCore<T>::sbc_a_xix() {
3037  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3038  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3039  T::setMemPtr(addr);
3040  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3041  return T::CC_DD + T::CC_CP_XIX;
3042 }
3043 
3044 // SUB r
3045 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3046  unsigned res = getA() - reg;
3047  byte f = ((res & 0x100) ? C_FLAG : 0) |
3048  N_FLAG |
3049  ((getA() ^ res ^ reg) & H_FLAG) |
3050  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3051  if (T::isR800()) {
3052  f |= ZSTable[res & 0xFF];
3053  f |= getF() & (X_FLAG | Y_FLAG);
3054  } else {
3055  f |= ZSXYTable[res & 0xFF];
3056  }
3057  setF(f);
3058  setA(res);
3059 }
3060 template<class T> int CPUCore<T>::sub_a() {
3061  if (T::isR800()) {
3062  word t = 0 * 256 | ZS0 | N_FLAG;
3063  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3064  } else {
3065  setAF(0 * 256 | ZSXY0 | N_FLAG);
3066  }
3067  return T::CC_CP_R;
3068 }
3069 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sub_R() {
3070  SUB(get8<SRC>()); return T::CC_CP_R + EE;
3071 }
3072 template<class T> int CPUCore<T>::sub_byte() {
3073  SUB(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3074 }
3075 template<class T> int CPUCore<T>::sub_xhl() {
3076  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3077 }
3078 template<class T> template<Reg16 IXY> int CPUCore<T>::sub_xix() {
3079  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3080  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3081  T::setMemPtr(addr);
3082  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3083  return T::CC_DD + T::CC_CP_XIX;
3084 }
3085 
3086 // XOR r
3087 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3088  setA(getA() ^ reg);
3089  byte f = 0;
3090  if (T::isR800()) {
3091  f |= ZSPTable[getA()];
3092  f |= getF() & (X_FLAG | Y_FLAG);
3093  } else {
3094  f |= ZSPXYTable[getA()];
3095  }
3096  setF(f);
3097 }
3098 template<class T> int CPUCore<T>::xor_a() {
3099  if (T::isR800()) {
3100  word t = 0 * 256 + ZSP0;
3101  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3102  } else {
3103  setAF(0 * 256 + ZSPXY0);
3104  }
3105  return T::CC_CP_R;
3106 }
3107 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::xor_R() {
3108  XOR(get8<SRC>()); return T::CC_CP_R + EE;
3109 }
3110 template<class T> int CPUCore<T>::xor_byte() {
3111  XOR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3112 }
3113 template<class T> int CPUCore<T>::xor_xhl() {
3114  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3115 }
3116 template<class T> template<Reg16 IXY> int CPUCore<T>::xor_xix() {
3117  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3118  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3119  T::setMemPtr(addr);
3120  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3121  return T::CC_DD + T::CC_CP_XIX;
3122 }
3123 
3124 
3125 // DEC r
3126 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3127  byte res = reg - 1;
3128  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3129  (((res & 0x0F) + 1) & H_FLAG) |
3130  N_FLAG;
3131  if (T::isR800()) {
3132  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3133  f |= ZSTable[res];
3134  } else {
3135  f |= getF() & C_FLAG;
3136  f |= ZSXYTable[res];
3137  }
3138  setF(f);
3139  return res;
3140 }
3141 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::dec_R() {
3142  set8<REG>(DEC(get8<REG>())); return T::CC_INC_R + EE;
3143 }
3144 template<class T> template<int EE> inline int CPUCore<T>::DEC_X(unsigned x) {
3145  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3146  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3147  return T::CC_INC_XHL + EE;
3148 }
3149 template<class T> int CPUCore<T>::dec_xhl() {
3150  return DEC_X<0>(getHL());
3151 }
3152 template<class T> template<Reg16 IXY> int CPUCore<T>::dec_xix() {
3153  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3154  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3155  T::setMemPtr(addr);
3156  return DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3157 }
3158 
3159 // INC r
3160 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3161  reg++;
3162  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3163  (((reg & 0x0F) - 1) & H_FLAG) |
3164  0; // N_FLAG
3165  if (T::isR800()) {
3166  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3167  f |= ZSTable[reg];
3168  } else {
3169  f |= getF() & C_FLAG;
3170  f |= ZSXYTable[reg];
3171  }
3172  setF(f);
3173  return reg;
3174 }
3175 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::inc_R() {
3176  set8<REG>(INC(get8<REG>())); return T::CC_INC_R + EE;
3177 }
3178 template<class T> template<int EE> inline int CPUCore<T>::INC_X(unsigned x) {
3179  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3180  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3181  return T::CC_INC_XHL + EE;
3182 }
3183 template<class T> int CPUCore<T>::inc_xhl() {
3184  return INC_X<0>(getHL());
3185 }
3186 template<class T> template<Reg16 IXY> int CPUCore<T>::inc_xix() {
3187  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3188  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3189  T::setMemPtr(addr);
3190  return INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3191 }
3192 
3193 
3194 // ADC HL,ss
3195 template<class T> template<Reg16 REG> inline int CPUCore<T>::adc_hl_SS() {
3196  unsigned reg = get16<REG>();
3197  T::setMemPtr(getHL() + 1);
3198  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3199  byte f = (res >> 16) | // C_FLAG
3200  0; // N_FLAG
3201  if (T::isR800()) {
3202  f |= getF() & (X_FLAG | Y_FLAG);
3203  }
3204  if (res & 0xFFFF) {
3205  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3206  f |= 0; // Z_FLAG
3207  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3208  if (T::isR800()) {
3209  f |= (res >> 8) & S_FLAG;
3210  } else {
3211  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3212  }
3213  } else {
3214  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3215  f |= Z_FLAG;
3216  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3217  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3218  }
3219  setF(f);
3220  setHL(res);
3221  return T::CC_ADC_HL_SS;
3222 }
3223 template<class T> int CPUCore<T>::adc_hl_hl() {
3224  T::setMemPtr(getHL() + 1);
3225  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3226  byte f = (res >> 16) | // C_FLAG
3227  0; // N_FLAG
3228  if (T::isR800()) {
3229  f |= getF() & (X_FLAG | Y_FLAG);
3230  }
3231  if (res & 0xFFFF) {
3232  f |= 0; // Z_FLAG
3233  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3234  if (T::isR800()) {
3235  f |= (res >> 8) & (H_FLAG | S_FLAG);
3236  } else {
3237  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3238  }
3239  } else {
3240  f |= Z_FLAG;
3241  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3242  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3243  }
3244  setF(f);
3245  setHL(res);
3246  return T::CC_ADC_HL_SS;
3247 }
3248 
3249 // ADD HL/IX/IY,ss
3250 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> int CPUCore<T>::add_SS_TT() {
3251  unsigned reg1 = get16<REG1>();
3252  unsigned reg2 = get16<REG2>();
3253  T::setMemPtr(reg1 + 1);
3254  unsigned res = reg1 + reg2;
3255  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3256  (res >> 16) | // C_FLAG
3257  0; // N_FLAG
3258  if (T::isR800()) {
3259  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3260  } else {
3261  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3262  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3263  }
3264  setF(f);
3265  set16<REG1>(res & 0xFFFF);
3266  return T::CC_ADD_HL_SS + EE;
3267 }
3268 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::add_SS_SS() {
3269  unsigned reg = get16<REG>();
3270  T::setMemPtr(reg + 1);
3271  unsigned res = 2 * reg;
3272  byte f = (res >> 16) | // C_FLAG
3273  0; // N_FLAG
3274  if (T::isR800()) {
3275  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3276  f |= (res >> 8) & H_FLAG;
3277  } else {
3278  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3279  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3280  }
3281  setF(f);
3282  set16<REG>(res & 0xFFFF);
3283  return T::CC_ADD_HL_SS + EE;
3284 }
3285 
3286 // SBC HL,ss
3287 template<class T> template<Reg16 REG> inline int CPUCore<T>::sbc_hl_SS() {
3288  unsigned reg = get16<REG>();
3289  T::setMemPtr(getHL() + 1);
3290  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3291  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3292  N_FLAG;
3293  if (T::isR800()) {
3294  f |= getF() & (X_FLAG | Y_FLAG);
3295  }
3296  if (res & 0xFFFF) {
3297  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3298  f |= 0; // Z_FLAG
3299  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3300  if (T::isR800()) {
3301  f |= (res >> 8) & S_FLAG;
3302  } else {
3303  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3304  }
3305  } else {
3306  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3307  f |= Z_FLAG;
3308  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3309  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3310  }
3311  setF(f);
3312  setHL(res);
3313  return T::CC_ADC_HL_SS;
3314 }
3315 template<class T> int CPUCore<T>::sbc_hl_hl() {
3316  T::setMemPtr(getHL() + 1);
3317  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3318  if (getF() & C_FLAG) {
3319  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3320  if (!T::isR800()) {
3321  f |= X_FLAG | Y_FLAG;
3322  }
3323  setHL(0xFFFF);
3324  } else {
3325  f |= Z_FLAG | N_FLAG;
3326  setHL(0);
3327  }
3328  setF(f);
3329  return T::CC_ADC_HL_SS;
3330 }
3331 
3332 // DEC ss
3333 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::dec_SS() {
3334  set16<REG>(get16<REG>() - 1); return T::CC_INC_SS + EE;
3335 }
3336 
3337 // INC ss
3338 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::inc_SS() {
3339  set16<REG>(get16<REG>() + 1); return T::CC_INC_SS + EE;
3340 }
3341 
3342 
3343 // BIT n,r
3344 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::bit_N_R() {
3345  byte reg = get8<REG>();
3346  byte f = 0; // N_FLAG
3347  if (T::isR800()) {
3348  // this is very different from Z80 (not only XY flags)
3349  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3350  f |= H_FLAG;
3351  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3352  } else {
3353  f |= ZSPHTable[reg & (1 << N)];
3354  f |= getF() & C_FLAG;
3355  f |= reg & (X_FLAG | Y_FLAG);
3356  }
3357  setF(f);
3358  return T::CC_BIT_R;
3359 }
3360 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xhl() {
3361  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3362  byte f = 0; // N_FLAG
3363  if (T::isR800()) {
3364  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3365  f |= H_FLAG;
3366  f |= m ? 0 : Z_FLAG;
3367  } else {
3368  f |= ZSPHTable[m];
3369  f |= getF() & C_FLAG;
3370  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3371  }
3372  setF(f);
3373  return T::CC_BIT_XHL;
3374 }
3375 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xix(unsigned addr) {
3376  T::setMemPtr(addr);
3377  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3378  byte f = 0; // N_FLAG
3379  if (T::isR800()) {
3380  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3381  f |= H_FLAG;
3382  f |= m ? 0 : Z_FLAG;
3383  } else {
3384  f |= ZSPHTable[m];
3385  f |= getF() & C_FLAG;
3386  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3387  }
3388  setF(f);
3389  return T::CC_DD + T::CC_BIT_XIX;
3390 }
3391 
3392 // RES n,r
3393 static inline byte RES(unsigned b, byte reg) {
3394  return reg & ~(1 << b);
3395 }
3396 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_R() {
3397  set8<REG>(RES(N, get8<REG>())); return T::CC_SET_R;
3398 }
3399 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3400  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3401  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3402  return res;
3403 }
3404 template<class T> template<unsigned N> int CPUCore<T>::res_N_xhl() {
3405  RES_X<0>(N, getHL()); return T::CC_SET_XHL;
3406 }
3407 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_xix_R(unsigned a) {
3408  T::setMemPtr(a);
3409  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3410  return T::CC_DD + T::CC_SET_XIX;
3411 }
3412 
3413 // SET n,r
3414 static inline byte SET(unsigned b, byte reg) {
3415  return reg | (1 << b);
3416 }
3417 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_R() {
3418  set8<REG>(SET(N, get8<REG>())); return T::CC_SET_R;
3419 }
3420 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3421  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3422  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3423  return res;
3424 }
3425 template<class T> template<unsigned N> int CPUCore<T>::set_N_xhl() {
3426  SET_X<0>(N, getHL()); return T::CC_SET_XHL;
3427 }
3428 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_xix_R(unsigned a) {
3429  T::setMemPtr(a);
3430  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3431  return T::CC_DD + T::CC_SET_XIX;
3432 }
3433 
3434 // RL r
3435 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3436  byte c = reg >> 7;
3437  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3438  byte f = c ? C_FLAG : 0;
3439  if (T::isR800()) {
3440  f |= ZSPTable[reg];
3441  f |= getF() & (X_FLAG | Y_FLAG);
3442  } else {
3443  f |= ZSPXYTable[reg];
3444  }
3445  setF(f);
3446  return reg;
3447 }
3448 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3449  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3450  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3451  return res;
3452 }
3453 template<class T> template<Reg8 REG> int CPUCore<T>::rl_R() {
3454  set8<REG>(RL(get8<REG>())); return T::CC_SET_R;
3455 }
3456 template<class T> int CPUCore<T>::rl_xhl() {
3457  RL_X<0>(getHL()); return T::CC_SET_XHL;
3458 }
3459 template<class T> template<Reg8 REG> int CPUCore<T>::rl_xix_R(unsigned a) {
3460  T::setMemPtr(a);
3461  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3462  return T::CC_DD + T::CC_SET_XIX;
3463 }
3464 
3465 // RLC r
3466 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3467  byte c = reg >> 7;
3468  reg = (reg << 1) | c;
3469  byte f = c ? C_FLAG : 0;
3470  if (T::isR800()) {
3471  f |= ZSPTable[reg];
3472  f |= getF() & (X_FLAG | Y_FLAG);
3473  } else {
3474  f |= ZSPXYTable[reg];
3475  }
3476  setF(f);
3477  return reg;
3478 }
3479 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3480  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3481  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3482  return res;
3483 }
3484 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_R() {
3485  set8<REG>(RLC(get8<REG>())); return T::CC_SET_R;
3486 }
3487 template<class T> int CPUCore<T>::rlc_xhl() {
3488  RLC_X<0>(getHL()); return T::CC_SET_XHL;
3489 }
3490 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_xix_R(unsigned a) {
3491  T::setMemPtr(a);
3492  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3493  return T::CC_DD + T::CC_SET_XIX;
3494 }
3495 
3496 // RR r
3497 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3498  byte c = reg & 1;
3499  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3500  byte f = c ? C_FLAG : 0;
3501  if (T::isR800()) {
3502  f |= ZSPTable[reg];
3503  f |= getF() & (X_FLAG | Y_FLAG);
3504  } else {
3505  f |= ZSPXYTable[reg];
3506  }
3507  setF(f);
3508  return reg;
3509 }
3510 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3511  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3512  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3513  return res;
3514 }
3515 template<class T> template<Reg8 REG> int CPUCore<T>::rr_R() {
3516  set8<REG>(RR(get8<REG>())); return T::CC_SET_R;
3517 }
3518 template<class T> int CPUCore<T>::rr_xhl() {
3519  RR_X<0>(getHL()); return T::CC_SET_XHL;
3520 }
3521 template<class T> template<Reg8 REG> int CPUCore<T>::rr_xix_R(unsigned a) {
3522  T::setMemPtr(a);
3523  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3524  return T::CC_DD + T::CC_SET_XIX;
3525 }
3526 
3527 // RRC r
3528 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3529  byte c = reg & 1;
3530  reg = (reg >> 1) | (c << 7);
3531  byte f = c ? C_FLAG : 0;
3532  if (T::isR800()) {
3533  f |= ZSPTable[reg];
3534  f |= getF() & (X_FLAG | Y_FLAG);
3535  } else {
3536  f |= ZSPXYTable[reg];
3537  }
3538  setF(f);
3539  return reg;
3540 }
3541 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3542  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3543  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3544  return res;
3545 }
3546 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_R() {
3547  set8<REG>(RRC(get8<REG>())); return T::CC_SET_R;
3548 }
3549 template<class T> int CPUCore<T>::rrc_xhl() {
3550  RRC_X<0>(getHL()); return T::CC_SET_XHL;
3551 }
3552 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_xix_R(unsigned a) {
3553  T::setMemPtr(a);
3554  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3555  return T::CC_DD + T::CC_SET_XIX;
3556 }
3557 
3558 // SLA r
3559 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3560  byte c = reg >> 7;
3561  reg <<= 1;
3562  byte f = c ? C_FLAG : 0;
3563  if (T::isR800()) {
3564  f |= ZSPTable[reg];
3565  f |= getF() & (X_FLAG | Y_FLAG);
3566  } else {
3567  f |= ZSPXYTable[reg];
3568  }
3569  setF(f);
3570  return reg;
3571 }
3572 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3573  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3574  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3575  return res;
3576 }
3577 template<class T> template<Reg8 REG> int CPUCore<T>::sla_R() {
3578  set8<REG>(SLA(get8<REG>())); return T::CC_SET_R;
3579 }
3580 template<class T> int CPUCore<T>::sla_xhl() {
3581  SLA_X<0>(getHL()); return T::CC_SET_XHL;
3582 }
3583 template<class T> template<Reg8 REG> int CPUCore<T>::sla_xix_R(unsigned a) {
3584  T::setMemPtr(a);
3585  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3586  return T::CC_DD + T::CC_SET_XIX;
3587 }
3588 
3589 // SLL r
3590 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3591  assert(!T::isR800()); // this instruction is Z80-only
3592  byte c = reg >> 7;
3593  reg = (reg << 1) | 1;
3594  byte f = c ? C_FLAG : 0;
3595  f |= ZSPXYTable[reg];
3596  setF(f);
3597  return reg;
3598 }
3599 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3600  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3601  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3602  return res;
3603 }
3604 template<class T> template<Reg8 REG> int CPUCore<T>::sll_R() {
3605  set8<REG>(SLL(get8<REG>())); return T::CC_SET_R;
3606 }
3607 template<class T> int CPUCore<T>::sll_xhl() {
3608  SLL_X<0>(getHL()); return T::CC_SET_XHL;
3609 }
3610 template<class T> template<Reg8 REG> int CPUCore<T>::sll_xix_R(unsigned a) {
3611  T::setMemPtr(a);
3612  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3613  return T::CC_DD + T::CC_SET_XIX;
3614 }
3615 template<class T> int CPUCore<T>::sll2() {
3616  assert(T::isR800()); // this instruction is R800-only
3617  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3618  (getA() >> 7) | // C_FLAG
3619  0; // all other flags zero
3620  setF(f);
3621  return T::CC_DD + T::CC_SET_XIX; // TODO
3622 }
3623 
3624 // SRA r
3625 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3626  byte c = reg & 1;
3627  reg = (reg >> 1) | (reg & 0x80);
3628  byte f = c ? C_FLAG : 0;
3629  if (T::isR800()) {
3630  f |= ZSPTable[reg];
3631  f |= getF() & (X_FLAG | Y_FLAG);
3632  } else {
3633  f |= ZSPXYTable[reg];
3634  }
3635  setF(f);
3636  return reg;
3637 }
3638 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3639  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3640  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3641  return res;
3642 }
3643 template<class T> template<Reg8 REG> int CPUCore<T>::sra_R() {
3644  set8<REG>(SRA(get8<REG>())); return T::CC_SET_R;
3645 }
3646 template<class T> int CPUCore<T>::sra_xhl() {
3647  SRA_X<0>(getHL()); return T::CC_SET_XHL;
3648 }
3649 template<class T> template<Reg8 REG> int CPUCore<T>::sra_xix_R(unsigned a) {
3650  T::setMemPtr(a);
3651  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3652  return T::CC_DD + T::CC_SET_XIX;
3653 }
3654 
3655 // SRL R
3656 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3657  byte c = reg & 1;
3658  reg >>= 1;
3659  byte f = c ? C_FLAG : 0;
3660  if (T::isR800()) {
3661  f |= ZSPTable[reg];
3662  f |= getF() & (X_FLAG | Y_FLAG);
3663  } else {
3664  f |= ZSPXYTable[reg];
3665  }
3666  setF(f);
3667  return reg;
3668 }
3669 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3670  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3671  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3672  return res;
3673 }
3674 template<class T> template<Reg8 REG> int CPUCore<T>::srl_R() {
3675  set8<REG>(SRL(get8<REG>())); return T::CC_SET_R;
3676 }
3677 template<class T> int CPUCore<T>::srl_xhl() {
3678  SRL_X<0>(getHL()); return T::CC_SET_XHL;
3679 }
3680 template<class T> template<Reg8 REG> int CPUCore<T>::srl_xix_R(unsigned a) {
3681  T::setMemPtr(a);
3682  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3683  return T::CC_DD + T::CC_SET_XIX;
3684 }
3685 
3686 // RLA RLCA RRA RRCA
3687 template<class T> int CPUCore<T>::rla() {
3688  byte c = getF() & C_FLAG;
3689  byte f = (getA() & 0x80) ? C_FLAG : 0;
3690  if (T::isR800()) {
3691  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3692  } else {
3693  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3694  }
3695  setA((getA() << 1) | (c ? 1 : 0));
3696  if (!T::isR800()) {
3697  f |= getA() & (X_FLAG | Y_FLAG);
3698  }
3699  setF(f);
3700  return T::CC_RLA;
3701 }
3702 template<class T> int CPUCore<T>::rlca() {
3703  setA((getA() << 1) | (getA() >> 7));
3704  byte f = 0;
3705  if (T::isR800()) {
3706  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3707  f |= getA() & C_FLAG;
3708  } else {
3709  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3710  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3711  }
3712  setF(f);
3713  return T::CC_RLA;
3714 }
3715 template<class T> int CPUCore<T>::rra() {
3716  byte c = (getF() & C_FLAG) << 7;
3717  byte f = (getA() & 0x01) ? C_FLAG : 0;
3718  if (T::isR800()) {
3719  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3720  } else {
3721  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3722  }
3723  setA((getA() >> 1) | c);
3724  if (!T::isR800()) {
3725  f |= getA() & (X_FLAG | Y_FLAG);
3726  }
3727  setF(f);
3728  return T::CC_RLA;
3729 }
3730 template<class T> int CPUCore<T>::rrca() {
3731  byte f = getA() & C_FLAG;
3732  if (T::isR800()) {
3733  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3734  } else {
3735  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3736  }
3737  setA((getA() >> 1) | (getA() << 7));
3738  if (!T::isR800()) {
3739  f |= getA() & (X_FLAG | Y_FLAG);
3740  }
3741  setF(f);
3742  return T::CC_RLA;
3743 }
3744 
3745 
3746 // RLD
3747 template<class T> int CPUCore<T>::rld() {
3748  byte val = RDMEM(getHL(), T::CC_RLD_1);
3749  T::setMemPtr(getHL() + 1);
3750  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3751  setA((getA() & 0xF0) | (val >> 4));
3752  byte f = 0;
3753  if (T::isR800()) {
3754  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3755  f |= ZSPTable[getA()];
3756  } else {
3757  f |= getF() & C_FLAG;
3758  f |= ZSPXYTable[getA()];
3759  }
3760  setF(f);
3761  return T::CC_RLD;
3762 }
3763 
3764 // RRD
3765 template<class T> int CPUCore<T>::rrd() {
3766  byte val = RDMEM(getHL(), T::CC_RLD_1);
3767  T::setMemPtr(getHL() + 1);
3768  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3769  setA((getA() & 0xF0) | (val & 0x0F));
3770  byte f = 0;
3771  if (T::isR800()) {
3772  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3773  f |= ZSPTable[getA()];
3774  } else {
3775  f |= getF() & C_FLAG;
3776  f |= ZSPXYTable[getA()];
3777  }
3778  setF(f);
3779  return T::CC_RLD;
3780 }
3781 
3782 
3783 // PUSH ss
3784 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3785  setSP(getSP() - 2);
3786  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3787 }
3788 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::push_SS() {
3789  PUSH<EE>(get16<REG>()); return T::CC_PUSH + EE;
3790 }
3791 
3792 // POP ss
3793 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3794  unsigned addr = getSP();
3795  setSP(addr + 2);
3796  return RD_WORD(addr, T::CC_POP_1 + EE);
3797 }
3798 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::pop_SS() {
3799  set16<REG>(POP<EE>()); return T::CC_POP + EE;
3800 }
3801 
3802 
3803 // CALL nn / CALL cc,nn
3804 template<class T> template<typename COND> int CPUCore<T>::call(COND cond) {
3805  unsigned addr = RD_WORD_PC(T::CC_CALL_1);
3806  T::setMemPtr(addr);
3807  if (cond(getF())) {
3808  PUSH<T::EE_CALL>(getPC());
3809  setPC(addr);
3810  return T::CC_CALL_A;
3811  } else {
3812  return T::CC_CALL_B;
3813  }
3814 }
3815 
3816 
3817 // RST n
3818 template<class T> template<unsigned ADDR> int CPUCore<T>::rst() {
3819  PUSH<0>(getPC());
3820  T::setMemPtr(ADDR);
3821  setPC(ADDR);
3822  return T::CC_RST;
3823 }
3824 
3825 
3826 // RET
3827 template<class T> template<int EE, typename COND> inline int CPUCore<T>::RET(COND cond) {
3828  if (cond(getF())) {
3829  unsigned addr = POP<EE>();
3830  T::setMemPtr(addr);
3831  setPC(addr);
3832  return T::CC_RET_A + EE;
3833  } else {
3834  return T::CC_RET_B + EE;
3835  }
3836 }
3837 template<class T> template<typename COND> int CPUCore<T>::ret(COND cond) {
3838  return RET<T::EE_RET_C>(cond);
3839 }
3840 template<class T> int CPUCore<T>::ret() {
3841  return RET<0>(CondTrue());
3842 }
3843 template<class T> int CPUCore<T>::retn() { // also reti
3844  setIFF1(getIFF2());
3845  setSlowInstructions();
3846  return RET<T::EE_RETN>(CondTrue());
3847 }
3848 
3849 
3850 // JP ss
3851 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::jp_SS() {
3852  setPC(get16<REG>()); T::R800ForcePageBreak(); return T::CC_JP_HL + EE;
3853 }
3854 
3855 // JP nn / JP cc,nn
3856 template<class T> template<typename COND> int CPUCore<T>::jp(COND cond) {
3857  unsigned addr = RD_WORD_PC(T::CC_JP_1);
3858  T::setMemPtr(addr);
3859  if (cond(getF())) {
3860  setPC(addr);
3861  T::R800ForcePageBreak();
3862  return T::CC_JP_A;
3863  } else {
3864  return T::CC_JP_B;
3865  }
3866 }
3867 
3868 // JR e
3869 template<class T> template<typename COND> int CPUCore<T>::jr(COND cond) {
3870  offset ofst = RDMEM_OPCODE(T::CC_JR_1);
3871  if (cond(getF())) {
3872  if ((getPC() & 0xFF) == 0) {
3873  // On R800, when this instruction is located in the
3874  // last two byte of a page (a page is a 256-byte
3875  // (aligned) memory block) and even if we jump back,
3876  // thus fetching the next opcode byte does not cause a
3877  // page-break, there still is one cycle overhead. It's
3878  // as-if there is a page-break.
3879  //
3880  // This could be explained by some (very limited)
3881  // pipeline behaviour in R800: it seems that the
3882  // decision to cause a page-break on the next
3883  // instruction is already made before the jump
3884  // destination address for the current instruction is
3885  // calculated (though a destination address in another
3886  // page is also a reason for a page-break).
3887  //
3888  // It's likely all instructions behave like this, but I
3889  // think we can get away with only explicitly emulating
3890  // this behaviour in the djnz and the jr (conditional
3891  // or not) instructions: all other instructions that
3892  // cause the PC to change in a non-incremental way do
3893  // already force a pagebreak for another reason, so
3894  // this effect is masked. Examples of such instructions
3895  // are: JP, RET, CALL, RST, all repeated block
3896  // instructions, accepting an IRQ, (are there more
3897  // instructions are events that change PC?)
3898  //
3899  // See doc/r800-djnz.txt for more details.
3900  T::R800ForcePageBreak();
3901  }
3902  setPC((getPC() + ofst) & 0xFFFF);
3903  T::setMemPtr(getPC());
3904  return T::CC_JR_A;
3905  } else {
3906  return T::CC_JR_B;
3907  }
3908 }
3909 
3910 // DJNZ e
3911 template<class T> int CPUCore<T>::djnz() {
3912  byte b = getB() - 1;
3913  setB(b);
3914  offset ofst = RDMEM_OPCODE(T::CC_JR_1 + T::EE_DJNZ);
3915  if (b) {
3916  if ((getPC() & 0xFF) == 0) {
3917  // See comment in jr()
3918  T::R800ForcePageBreak();
3919  }
3920  setPC((getPC() + ofst) & 0xFFFF);
3921  T::setMemPtr(getPC());
3922  return T::CC_JR_A + T::EE_DJNZ;
3923  } else {
3924  return T::CC_JR_B + T::EE_DJNZ;
3925  }
3926 }
3927 
3928 // EX (SP),ss
3929 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ex_xsp_SS() {
3930  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3931  T::setMemPtr(res);
3932  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3933  set16<REG>(res);
3934  return T::CC_EX_SP_HL + EE;
3935 }
3936 
3937 // IN r,(c)
3938 template<class T> template<Reg8 REG> int CPUCore<T>::in_R_c() {
3939  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
3940  T::setMemPtr(getBC() + 1);
3941  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
3942  byte f = 0;
3943  if (T::isR800()) {
3944  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3945  f |= ZSPTable[res];
3946  } else {
3947  f |= getF() & C_FLAG;
3948  f |= ZSPXYTable[res];
3949  }
3950  setF(f);
3951  set8<REG>(res);
3952  return T::CC_IN_R_C;
3953 }
3954 
3955 // IN a,(n)
3956 template<class T> int CPUCore<T>::in_a_byte() {
3957  unsigned y = RDMEM_OPCODE(T::CC_IN_A_N_1) + 256 * getA();
3958  T::setMemPtr(y + 1);
3959  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
3960  setA(READ_PORT(y, T::CC_IN_A_N_2));
3961  return T::CC_IN_A_N;
3962 }
3963 
3964 // OUT (c),r
3965 template<class T> template<Reg8 REG> int CPUCore<T>::out_c_R() {
3966  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3967  T::setMemPtr(getBC() + 1);
3968  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
3969  return T::CC_OUT_C_R;
3970 }
3971 template<class T> int CPUCore<T>::out_c_0() {
3972  // TODO not on R800
3973  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3974  T::setMemPtr(getBC() + 1);
3975  byte out_c_x = isTurboR ? 255 : 0;
3976  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
3977  return T::CC_OUT_C_R;
3978 }
3979 
3980 // OUT (n),a
3981 template<class T> int CPUCore<T>::out_byte_a() {
3982  byte port = RDMEM_OPCODE(T::CC_OUT_N_A_1);
3983  unsigned y = (getA() << 8) | port;
3984  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
3985  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
3986  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
3987  return T::CC_OUT_N_A;
3988 }
3989 
3990 
3991 // block CP
3992 template<class T> inline int CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
3993  T::setMemPtr(T::getMemPtr() + increase);
3994  byte val = RDMEM(getHL(), T::CC_CPI_1);
3995  byte res = getA() - val;
3996  setHL(getHL() + increase);
3997  setBC(getBC() - 1);
3998  byte f = ((getA() ^ val ^ res) & H_FLAG) |
3999  ZSTable[res] |
4000  N_FLAG |
4001  (getBC() ? V_FLAG : 0);
4002  if (T::isR800()) {
4003  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4004  } else {
4005  f |= getF() & C_FLAG;
4006  unsigned k = res - ((f & H_FLAG) >> 4);
4007  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4008  f |= k & X_FLAG; // bit 3 -> flag 3
4009  }
4010  setF(f);
4011  if (repeat && getBC() && res) {
4012  setPC(getPC() - 2);
4013  T::setMemPtr(getPC() + 1);
4014  return T::CC_CPIR;
4015  } else {
4016  return T::CC_CPI;
4017  }
4018 }
4019 template<class T> int CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4020 template<class T> int CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4021 template<class T> int CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4022 template<class T> int CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4023 
4024 
4025 // block LD
4026 template<class T> inline int CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4027  byte val = RDMEM(getHL(), T::CC_LDI_1);
4028  WRMEM(getDE(), val, T::CC_LDI_2);
4029  setHL(getHL() + increase);
4030  setDE(getDE() + increase);
4031  setBC(getBC() - 1);
4032  byte f = getBC() ? V_FLAG : 0;
4033  if (T::isR800()) {
4034  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4035  } else {
4036  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4037  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4038  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4039  }
4040  setF(f);
4041  if (repeat && getBC()) {
4042  setPC(getPC() - 2);
4043  T::setMemPtr(getPC() + 1);
4044  return T::CC_LDIR;
4045  } else {
4046  return T::CC_LDI;
4047  }
4048 }
4049 template<class T> int CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4050 template<class T> int CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4051 template<class T> int CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4052 template<class T> int CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4053 
4054 
4055 // block IN
4056 template<class T> inline int CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4057  // TODO R800 flags
4058  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4059  T::setMemPtr(getBC() + increase);
4060  setBC(getBC() - 0x100); // decr before use
4061  byte val = READ_PORT(getBC(), T::CC_INI_1);
4062  WRMEM(getHL(), val, T::CC_INI_2);
4063  setHL(getHL() + increase);
4064  unsigned k = val + ((getC() + increase) & 0xFF);
4065  byte b = getB();
4066  setF(((val & S_FLAG) >> 6) | // N_FLAG
4067  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4068  ZSXYTable[b] |
4069  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4070  if (repeat && b) {
4071  setPC(getPC() - 2);
4072  return T::CC_INIR;
4073  } else {
4074  return T::CC_INI;
4075  }
4076 }
4077 template<class T> int CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4078 template<class T> int CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4079 template<class T> int CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4080 template<class T> int CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4081 
4082 
4083 // block OUT
4084 template<class T> inline int CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4085  // TODO R800 flags
4086  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4087  setHL(getHL() + increase);
4088  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4089  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4090  setBC(getBC() - 0x100); // decr after use
4091  T::setMemPtr(getBC() + increase);
4092  unsigned k = val + getL();
4093  byte b = getB();
4094  setF(((val & S_FLAG) >> 6) | // N_FLAG
4095  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4096  ZSXYTable[b] |
4097  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4098  if (repeat && b) {
4099  setPC(getPC() - 2);
4100  return T::CC_OTIR;
4101  } else {
4102  return T::CC_OUTI;
4103  }
4104 }
4105 template<class T> int CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4106 template<class T> int CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4107 template<class T> int CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4108 template<class T> int CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4109 
4110 
4111 // various
4112 template<class T> int CPUCore<T>::nop() { return T::CC_NOP; }
4113 template<class T> int CPUCore<T>::ccf() {
4114  byte f = 0;
4115  if (T::isR800()) {
4116  // H flag is different from Z80 (and as always XY flags as well)
4117  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4118  } else {
4119  f |= (getF() & C_FLAG) << 4; // H_FLAG
4120  // only set X(Y) flag (don't reset if already set)
4121  if (isTurboR) {
4122  // Y flag is not changed on a turboR-Z80
4123  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4124  f |= (getF() | getA()) & X_FLAG;
4125  } else {
4126  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4127  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4128  }
4129  }
4130  f ^= C_FLAG;
4131  setF(f);
4132  return T::CC_CCF;
4133 }
4134 template<class T> int CPUCore<T>::cpl() {
4135  setA(getA() ^ 0xFF);
4136  byte f = H_FLAG | N_FLAG;
4137  if (T::isR800()) {
4138  f |= getF();
4139  } else {
4140  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4141  f |= getA() & (X_FLAG | Y_FLAG);
4142  }
4143  setF(f);
4144  return T::CC_CPL;
4145 }
4146 template<class T> int CPUCore<T>::daa() {
4147  byte a = getA();
4148  byte f = getF();
4149  byte adjust = 0;
4150  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4151  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4152  if (f & N_FLAG) a -= adjust; else a += adjust;
4153  if (T::isR800()) {
4154  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4155  f |= ZSPTable[a];
4156  } else {
4157  f &= C_FLAG | N_FLAG;
4158  f |= ZSPXYTable[a];
4159  }
4160  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4161  setA(a);
4162  setF(f);
4163  return T::CC_DAA;
4164 }
4165 template<class T> int CPUCore<T>::neg() {
4166  // alternative: LUT word negTable[256]
4167  unsigned a = getA();
4168  unsigned res = -signed(a);
4169  byte f = ((res & 0x100) ? C_FLAG : 0) |
4170  N_FLAG |
4171  ((res ^ a) & H_FLAG) |
4172  ((a & res & 0x80) >> 5); // V_FLAG
4173  if (T::isR800()) {
4174  f |= ZSTable[res & 0xFF];
4175  f |= getF() & (X_FLAG | Y_FLAG);
4176  } else {
4177  f |= ZSXYTable[res & 0xFF];
4178  }
4179  setF(f);
4180  setA(res);
4181  return T::CC_NEG;
4182 }
4183 template<class T> int CPUCore<T>::scf() {
4184  byte f = C_FLAG;
4185  if (T::isR800()) {
4186  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4187  } else {
4188  // only set X(Y) flag (don't reset if already set)
4189  if (isTurboR) {
4190  // Y flag is not changed on a turboR-Z80
4191  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4192  f |= (getF() | getA()) & X_FLAG;
4193  } else {
4194  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4195  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4196  }
4197  }
4198  setF(f);
4199  return T::CC_SCF;
4200 }
4201 
4202 template<class T> int CPUCore<T>::ex_af_af() {
4203  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4204  return T::CC_EX;
4205 }
4206 template<class T> int CPUCore<T>::ex_de_hl() {
4207  unsigned t = getDE(); setDE(getHL()); setHL(t);
4208  return T::CC_EX;
4209 }
4210 template<class T> int CPUCore<T>::exx() {
4211  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4212  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4213  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4214  return T::CC_EX;
4215 }
4216 
4217 template<class T> int CPUCore<T>::di() {
4218  setIFF1(false);
4219  setIFF2(false);
4220  return T::CC_DI;
4221 }
4222 template<class T> int CPUCore<T>::ei() {
4223  setIFF1(true);
4224  setIFF2(true);
4225  setAfterEI(); // no ints directly after this instr
4226  setSlowInstructions();
4227  return T::CC_EI;
4228 }
4229 template<class T> int CPUCore<T>::halt() {
4230  setHALT(true);
4231  setSlowInstructions();
4232 
4233  if (!(getIFF1() || getIFF2())) {
4234  diHaltCallback.execute();
4235  }
4236  return T::CC_HALT;
4237 }
4238 template<class T> template<unsigned N> int CPUCore<T>::im_N() {
4239  setIM(N); return T::CC_IM;
4240 }
4241 
4242 // LD A,I/R
4243 template<class T> template<Reg8 REG> int CPUCore<T>::ld_a_IR() {
4244  setA(get8<REG>());
4245  byte f = getIFF2() ? V_FLAG : 0;
4246  if (T::isR800()) {
4247  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4248  f |= ZSTable[getA()];
4249  } else {
4250  f |= getF() & C_FLAG;
4251  f |= ZSXYTable[getA()];
4252  // see comment in the IRQ acceptance part of executeSlow().
4253  setAfterLDAI(); // only Z80 (not R800) has this quirk
4254  setSlowInstructions();
4255  }
4256  setF(f);
4257  return T::CC_LD_A_I;
4258 }
4259 
4260 // LD I/R,A
4261 template<class T> int CPUCore<T>::ld_r_a() {
4262  // This code sequence:
4263  // XOR A / LD R,A / LD A,R
4264  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4265  // explained by a difference in the relative time between writing the
4266  // new value to the R register and increasing the R register per M1
4267  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4268  // R, that's good enough for now.
4269  byte val = getA();
4270  if (T::isR800()) val -= 1;
4271  setR(val);
4272  return T::CC_LD_A_I;
4273 }
4274 template<class T> int CPUCore<T>::ld_i_a() {
4275  setI(getA());
4276  return T::CC_LD_A_I;
4277 }
4278 
4279 // MULUB A,r
4280 template<class T> template<Reg8 REG> int CPUCore<T>::mulub_a_R() {
4281  assert(T::isR800()); // this instruction is R800-only
4282  // Verified on real R800:
4283  // YHXN flags are unchanged
4284  // SV flags are reset
4285  // Z flag is set when result is zero
4286  // C flag is set when result doesn't fit in 8-bit
4287  setHL(unsigned(getA()) * get8<REG>());
4288  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4289  0 | // S_FLAG V_FLAG
4290  (getHL() ? 0 : Z_FLAG) |
4291  ((getHL() & 0xFF00) ? C_FLAG : 0));
4292  return T::CC_MULUB;
4293 }
4294 
4295 // MULUW HL,ss
4296 template<class T> template<Reg16 REG> int CPUCore<T>::muluw_hl_SS() {
4297  assert(T::isR800()); // this instruction is R800-only
4298  // Verified on real R800:
4299  // YHXN flags are unchanged
4300  // SV flags are reset
4301  // Z flag is set when result is zero
4302  // C flag is set when result doesn't fit in 16-bit
4303  unsigned res = unsigned(getHL()) * get16<REG>();
4304  setDE(res >> 16);
4305  setHL(res & 0xffff);
4306  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4307  0 | // S_FLAG V_FLAG
4308  (res ? 0 : Z_FLAG) |
4309  ((res & 0xFFFF0000) ? C_FLAG : 0));
4310  return T::CC_MULUW;
4311 }
4312 
4313 
4314 // versions:
4315 // 1 -> initial version
4316 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4317 // 3 -> timing of the emulation changed (no changes in serialization)
4318 template<class T> template<typename Archive>
4319 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4320 {
4321  T::serialize(ar, version);
4322  ar.serialize("regs", static_cast<CPURegs&>(*this));
4323  if (ar.versionBelow(version, 2)) {
4324  unsigned memptr = 0; // dummy value (avoid warning)
4325  ar.serialize("memptr", memptr);
4326  T::setMemPtr(memptr);
4327  }
4328 
4329  if (ar.isLoader()) {
4330  invalidateMemCache(0x0000, 0x10000);
4331  }
4332 
4333  // don't serialize
4334  // IRQStatus
4335  // NMIStatus, nmiEdge
4336  // slowInstructions
4337  // exitLoop
4338 
4339  if (T::isR800() && ar.versionBelow(version, 3)) {
4340  motherboard.getMSXCliComm().printWarning(
4341  "Loading an old savestate: the timing of the R800 "
4342  "emulation has changed. This may cause synchronization "
4343  "problems in replay.");
4344  }
4345 }
4346 
4347 // Force template instantiation
4348 template class CPUCore<Z80TYPE>;
4349 template class CPUCore<R800TYPE>;
4350 
4353 
4354 } // namespace openmsx
signed char offset
Definition: CPUCore.cc:252
#define CASE(X)
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:363
bool operator()(byte f) const
Definition: CPUCore.cc:263
bool operator()(byte f) const
Definition: CPUCore.cc:261
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:348
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:489
size_type size() const
Definition: array_ref.hh:61
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:428
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:550
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:33
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:523
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:483
bool operator()(byte f) const
Definition: CPUCore.cc:267
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
bool operator()(byte f) const
Definition: CPUCore.cc:264
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:300
bool operator()(byte f) const
Definition: CPUCore.cc:262
bool operator()(byte) const
Definition: CPUCore.cc:269
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:433
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:507
#define NEXT
#define NEXT_STOP
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
A Setting with an integer value.
bool operator()(byte f) const
Definition: CPUCore.cc:265
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:38
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:455
void waitCycles(unsigned cycles)
Definition: CPUCore.cc:502
static const int CLOCK_FREQ
Definition: Z80.hh:17
bool operator()(byte f) const
Definition: CPUCore.cc:268
void execute(bool fastForward)
Definition: CPUCore.cc:2510
void addListElement(string_ref element)
Definition: TclObject.cc:110
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:464
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void wait(EmuTime::param time)
Definition: CPUCore.cc:495
#define NEXT_EI
size_t size() const
void warp(EmuTime::param time)
Definition: CPUCore.cc:342
#define likely(x)
Definition: likely.hh:14
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4319
bool operator()(byte f) const
Definition: CPUCore.cc:266
std::unique_ptr< T > make_unique()
Definition: memory.hh:27
void serialize(Archive &ar, T &t, unsigned version)
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:470
static bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:19
void invalidateMemCache(unsigned start, unsigned size)
Definition: CPUCore.cc:353
#define UNREACHABLE
Definition: unreachable.hh:56