openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include <iomanip>
176 #include <iostream>
177 #include <type_traits>
178 #include <cassert>
179 #include <cstring>
180 
181 
182 //
183 // #define USE_COMPUTED_GOTO
184 //
185 // Computed goto's are not enabled by default:
186 // - Computed goto's are a gcc extension, it's not part of the official c++
187 // standard. So this will only work if you use gcc as your compiler (it
188 // won't work with visual c++ for example)
189 // - This is only beneficial on CPUs with branch prediction for indirect jumps
190 // and a reasonable amout of cache. For example it is very benefical for a
191 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
192 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
193 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
194 // But even on more recent gcc versions it still requires around 700MB.
195 //
196 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
197 // flag to the compiler. This is for example done in the super-opt flavour.
198 // See build/flavour-super-opt.mk
199 
200 
201 using std::string;
202 
203 namespace openmsx {
204 
205 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
206 // As a quick hack I put these two lines here because I found it overkill to
207 // create two files each containing only a single line.
208 // Technically these two lines _are_ required according to the c++ standard.
209 // Though usually it works just find without them, but during experiments I did
210 // get a link error when these lines were missing (it only happened during a
211 // debug build with some specific compiler version and only with some
212 // combination of other code changes, but again when strictly following the
213 // language rules, these lines should be here).
214 // ... But visual studio is not fully standard compliant, see also comment
215 // in SectorAccesibleDisk.cc
216 #ifndef _MSC_VER
217 const int Z80TYPE ::CLOCK_FREQ;
218 const int R800TYPE::CLOCK_FREQ;
219 #endif
220 
221 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
222 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
223 
224 // flag positions
225 static const byte S_FLAG = 0x80;
226 static const byte Z_FLAG = 0x40;
227 static const byte Y_FLAG = 0x20;
228 static const byte H_FLAG = 0x10;
229 static const byte X_FLAG = 0x08;
230 static const byte V_FLAG = 0x04;
231 static const byte P_FLAG = V_FLAG;
232 static const byte N_FLAG = 0x02;
233 static const byte C_FLAG = 0x01;
234 
235 // flag-register tables, initialized at run-time
236 static byte ZSTable[256];
237 static byte ZSXYTable[256];
238 static byte ZSPTable[256];
239 static byte ZSPXYTable[256];
240 static byte ZSPHTable[256];
241 
242 static const byte ZS0 = Z_FLAG;
243 static const byte ZSXY0 = Z_FLAG;
244 static const byte ZSP0 = Z_FLAG | V_FLAG;
245 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
246 static const byte ZS255 = S_FLAG;
247 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
248 
249 typedef signed char offset;
250 
251 // Global variable, because it should be shared between Z80 and R800.
252 // It must not be shared between the CPUs of different MSX machines, but
253 // the (logical) lifetime of this variable cannot overlap between execution
254 // of two MSX machines.
255 static word start_pc;
256 
257 // conditions
258 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
259 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
260 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
261 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
262 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
263 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
264 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
265 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
266 struct CondTrue { bool operator()(byte) const { return true; } };
267 
268 static void initTables()
269 {
270  static bool alreadyInit = false;
271  if (alreadyInit) return;
272  alreadyInit = true;
273 
274  for (int i = 0; i < 256; ++i) {
275  byte zFlag = (i == 0) ? Z_FLAG : 0;
276  byte sFlag = i & S_FLAG;
277  byte xFlag = i & X_FLAG;
278  byte yFlag = i & Y_FLAG;
279  byte vFlag = V_FLAG;
280  for (int v = 128; v != 0; v >>= 1) {
281  if (i & v) vFlag ^= V_FLAG;
282  }
283  ZSTable [i] = zFlag | sFlag;
284  ZSXYTable [i] = zFlag | sFlag | xFlag | yFlag;
285  ZSPTable [i] = zFlag | sFlag | vFlag;
286  ZSPXYTable[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
287  ZSPHTable [i] = zFlag | sFlag | vFlag | H_FLAG;
288  }
289  assert(ZSTable [ 0] == ZS0);
290  assert(ZSXYTable [ 0] == ZSXY0);
291  assert(ZSPTable [ 0] == ZSP0);
292  assert(ZSPXYTable[ 0] == ZSPXY0);
293  assert(ZSTable [255] == ZS255);
294  assert(ZSXYTable [255] == ZSXY255);
295 }
296 
297 template<class T> CPUCore<T>::CPUCore(
298  MSXMotherBoard& motherboard_, const string& name,
299  const BooleanSetting& traceSetting_,
300  TclCallback& diHaltCallback_, EmuTime::param time)
301  : CPURegs(T::isR800())
302  , T(time, motherboard_.getScheduler())
303  , motherboard(motherboard_)
304  , scheduler(motherboard.getScheduler())
305  , interface(nullptr)
306  , traceSetting(traceSetting_)
307  , diHaltCallback(diHaltCallback_)
308  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
309  "Non-zero if there are pending IRQs (thus CPU would enter "
310  "interrupt routine in EI mode).",
311  0)
312  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
313  "This probe is only useful to set a breakpoint on (the value "
314  "return by read is meaningless). The breakpoint gets triggered "
315  "right after the CPU accepted an IRQ.")
316  , freqLocked(
317  motherboard.getCommandController(), name + "_freq_locked",
318  "real (locked) or custom (unlocked) " + name + " frequency",
319  true)
320  , freqValue(
321  motherboard.getCommandController(), name + "_freq",
322  "custom " + name + " frequency (only valid when unlocked)",
323  T::CLOCK_FREQ, 1000000, 1000000000)
324  , freq(T::CLOCK_FREQ)
325  , NMIStatus(0)
326  , nmiEdge(false)
327  , exitLoop(false)
328  , tracingEnabled(traceSetting.getBoolean())
329  , isTurboR(motherboard.isTurboR())
330 {
331  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
332  "keep CPUCore non-virtual to keep PC at offset 0");
333  doSetFreq();
334  doReset(time);
335 
336  initTables();
337 }
338 
339 template<class T> void CPUCore<T>::warp(EmuTime::param time)
340 {
341  assert(T::getTimeFast() <= time);
342  T::setTime(time);
343 }
344 
346 {
347  return T::getTime();
348 }
349 
350 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
351 {
352  unsigned first = start / CacheLine::SIZE;
353  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
354  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
355  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
356  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
357  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
358 }
359 
360 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
361 {
362  // AF and SP are 0xFFFF
363  // PC, R, IFF1, IFF2, HALT and IM are 0x0
364  // all others are random
365  setAF(0xFFFF);
366  setBC(0xFFFF);
367  setDE(0xFFFF);
368  setHL(0xFFFF);
369  setIX(0xFFFF);
370  setIY(0xFFFF);
371  setPC(0x0000);
372  setSP(0xFFFF);
373  setAF2(0xFFFF);
374  setBC2(0xFFFF);
375  setDE2(0xFFFF);
376  setHL2(0xFFFF);
377  clearNextAfter();
378  copyNextAfter();
379  setIFF1(false);
380  setIFF2(false);
381  setHALT(false);
382  setExtHALT(false);
383  setIM(0);
384  setI(0x00);
385  setR(0x00);
386  T::setMemPtr(0xFFFF);
387  invalidateMemCache(0x0000, 0x10000);
388 
389  // We expect this assert to be valid
390  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
391  // But it's disabled for the following reason:
392  // 'motion' (IRC nickname) managed to create a replay file that
393  // contains a reset command that falls in the middle of a Z80
394  // instruction. Replayed commands go via the Scheduler, and are
395  // (typically) executed right after a complete CPU instruction. So
396  // the CPU is (slightly) ahead in time of the about to be executed
397  // reset command.
398  // Normally this situation should never occur: console commands,
399  // hotkeys, commands over clicomm, ... are all handled via the global
400  // event mechanism. Such global events are scheduled between CPU
401  // instructions, so also in a replay they should fall between CPU
402  // instructions.
403  // However if for some reason the timing of the emulation changed
404  // (improved emulation accuracy or a bug so that emulation isn't
405  // deterministic or the replay file was edited, ...), then the above
406  // reasoning no longer holds and the assert can trigger.
407  // We need to be robust against loading older replays (when emulation
408  // timing has changed). So in that respect disabling the assert is
409  // good. Though in the example above (motion's replay) it's not clear
410  // whether the assert is really triggered by mixing an old replay
411  // with a newer openMSX version. In any case so far we haven't been
412  // able to reproduce this assert by recording and replaying using a
413  // single openMSX version.
414  T::setTime(time);
415 
416  assert(NMIStatus == 0); // other devices must reset their NMI source
417  assert(IRQStatus == 0); // other devices must reset their IRQ source
418 }
419 
420 // I believe the following two methods are thread safe even without any
421 // locking. The worst that can happen is that we occasionally needlessly
422 // exit the CPU loop, but that's harmless
423 // TODO thread issues are always tricky, can someone confirm this really
424 // is thread safe
425 template<class T> void CPUCore<T>::exitCPULoopAsync()
426 {
427  // can get called from non-main threads
428  exitLoop = true;
429 }
430 template<class T> void CPUCore<T>::exitCPULoopSync()
431 {
432  assert(Thread::isMainThread());
433  exitLoop = true;
434  T::disableLimit();
435 }
436 template<class T> inline bool CPUCore<T>::needExitCPULoop()
437 {
438  // always executed in main thread
439  if (unlikely(exitLoop)) {
440  exitLoop = false;
441  return true;
442  }
443  return false;
444 }
445 
446 template<class T> void CPUCore<T>::setSlowInstructions()
447 {
448  slowInstructions = 2;
449  T::disableLimit();
450 }
451 
452 template<class T> void CPUCore<T>::raiseIRQ()
453 {
454  assert(IRQStatus >= 0);
455  if (IRQStatus == 0) {
456  setSlowInstructions();
457  }
458  IRQStatus = IRQStatus + 1;
459 }
460 
461 template<class T> void CPUCore<T>::lowerIRQ()
462 {
463  IRQStatus = IRQStatus - 1;
464  assert(IRQStatus >= 0);
465 }
466 
467 template<class T> void CPUCore<T>::raiseNMI()
468 {
469  // NMIs are currently disabled, they are anyway not used in MSX and
470  // not having to check for them allows to emulate slightly faster
471  UNREACHABLE;
472  assert(NMIStatus >= 0);
473  if (NMIStatus == 0) {
474  nmiEdge = true;
475  setSlowInstructions();
476  }
477  NMIStatus++;
478 }
479 
480 template<class T> void CPUCore<T>::lowerNMI()
481 {
482  NMIStatus--;
483  assert(NMIStatus >= 0);
484 }
485 
486 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
487 {
488  // PC was already increased, so decrease again
489  return address == ((getPC() - 1) & 0xFFFF);
490 }
491 
492 template<class T> void CPUCore<T>::wait(EmuTime::param time)
493 {
494  assert(time >= getCurrentTime());
495  scheduler.schedule(time);
496  T::advanceTime(time);
497 }
498 
499 template<class T> void CPUCore<T>::waitCycles(unsigned cycles)
500 {
501  T::add(cycles);
502 }
503 
504 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
505 {
506  T::setLimit(time);
507 }
508 
509 
510 static inline char toHex(byte x)
511 {
512  return (x < 10) ? (x + '0') : (x - 10 + 'A');
513 }
514 static void toHex(byte x, char* buf)
515 {
516  buf[0] = toHex(x / 16);
517  buf[1] = toHex(x & 15);
518 }
519 
520 template<class T> void CPUCore<T>::disasmCommand(
521  Interpreter& interp, array_ref<TclObject> tokens, TclObject& result) const
522 {
523  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
524  byte outBuf[4];
525  std::string dasmOutput;
526  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
527  T::getTimeFast());
528  result.addListElement(dasmOutput);
529  char tmp[3]; tmp[2] = 0;
530  for (unsigned i = 0; i < len; ++i) {
531  toHex(outBuf[i], tmp);
532  result.addListElement(tmp);
533  }
534 }
535 
536 template<class T> void CPUCore<T>::update(const Setting& setting)
537 {
538  if (&setting == &freqLocked) {
539  doSetFreq();
540  } else if (&setting == &freqValue) {
541  doSetFreq();
542  } else if (&setting == &traceSetting) {
543  tracingEnabled = traceSetting.getBoolean();
544  }
545 }
546 
547 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
548 {
549  freq = freq_;
550  doSetFreq();
551 }
552 
553 template<class T> void CPUCore<T>::doSetFreq()
554 {
555  if (freqLocked.getBoolean()) {
556  // locked, use value set via setFreq()
557  T::setFreq(freq);
558  } else {
559  // unlocked, use value set by user
560  T::setFreq(freqValue.getInt());
561  }
562 }
563 
564 
565 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
566 {
567  EmuTime time = T::getTimeFast(cc);
568  scheduler.schedule(time);
569  byte result = interface->readIO(port, time);
570  // note: no forced page-break after IO
571  return result;
572 }
573 
574 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
575 {
576  EmuTime time = T::getTimeFast(cc);
577  scheduler.schedule(time);
578  interface->writeIO(port, value, time);
579  // note: no forced page-break after IO
580 }
581 
582 template<class T> template<bool PRE_PB, bool POST_PB>
583 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
584 {
585  // not cached
586  unsigned high = address >> CacheLine::BITS;
587  if (!readCacheTried[high]) {
588  // try to cache now
589  unsigned addrBase = address & CacheLine::HIGH;
590  if (const byte* line = interface->getReadCacheLine(addrBase)) {
591  // cached ok
592  T::template PRE_MEM<PRE_PB, POST_PB>(address);
593  T::template POST_MEM< POST_PB>(address);
594  readCacheLine[high] = line - addrBase;
595  return readCacheLine[high][address];
596  }
597  }
598  // uncacheable
599  readCacheTried[high] = true;
600  T::template PRE_MEM<PRE_PB, POST_PB>(address);
601  EmuTime time = T::getTimeFast(cc);
602  scheduler.schedule(time);
603  byte result = interface->readMem(address, time);
604  T::template POST_MEM<POST_PB>(address);
605  return result;
606 }
607 template<class T> template<bool PRE_PB, bool POST_PB>
608 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
609 {
610  const byte* line = readCacheLine[address >> CacheLine::BITS];
611  if (likely(line != nullptr)) {
612  // cached, fast path
613  T::template PRE_MEM<PRE_PB, POST_PB>(address);
614  T::template POST_MEM< POST_PB>(address);
615  return line[address];
616  } else {
617  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
618  }
619 }
620 template<class T> template<bool PRE_PB, bool POST_PB>
621 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
622 {
623  static const bool PRE = T::template Normalize<PRE_PB >::value;
624  static const bool POST = T::template Normalize<POST_PB>::value;
625  return RDMEM_impl2<PRE, POST>(address, cc);
626 }
627 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
628 {
629  unsigned address = getPC();
630  setPC(address + 1);
631  return RDMEM_impl<false, false>(address, cc);
632 }
633 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
634 {
635  return RDMEM_impl<true, true>(address, cc);
636 }
637 
638 template<class T> template<bool PRE_PB, bool POST_PB>
639 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
640 {
641  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
642  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
643  return res;
644 }
645 template<class T> template<bool PRE_PB, bool POST_PB>
646 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
647 {
648  const byte* line = readCacheLine[address >> CacheLine::BITS];
649  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
650  // fast path: cached and two bytes in same cache line
651  T::template PRE_WORD<PRE_PB, POST_PB>(address);
652  T::template POST_WORD< POST_PB>(address);
653  return Endian::read_UA_L16(&line[address]);
654  } else {
655  // slow path, not inline
656  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
657  }
658 }
659 template<class T> template<bool PRE_PB, bool POST_PB>
660 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
661 {
662  static const bool PRE = T::template Normalize<PRE_PB >::value;
663  static const bool POST = T::template Normalize<POST_PB>::value;
664  return RD_WORD_impl2<PRE, POST>(address, cc);
665 }
666 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
667 {
668  unsigned addr = getPC();
669  setPC(addr + 2);
670  return RD_WORD_impl<false, false>(addr, cc);
671 }
672 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
673  unsigned address, unsigned cc)
674 {
675  return RD_WORD_impl<true, true>(address, cc);
676 }
677 
678 template<class T> template<bool PRE_PB, bool POST_PB>
679 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
680 {
681  // not cached
682  unsigned high = address >> CacheLine::BITS;
683  if (!writeCacheTried[high]) {
684  // try to cache now
685  unsigned addrBase = address & CacheLine::HIGH;
686  if (byte* line = interface->getWriteCacheLine(addrBase)) {
687  // cached ok
688  T::template PRE_MEM<PRE_PB, POST_PB>(address);
689  T::template POST_MEM< POST_PB>(address);
690  writeCacheLine[high] = line - addrBase;
691  writeCacheLine[high][address] = value;
692  return;
693  }
694  }
695  // uncacheable
696  writeCacheTried[high] = true;
697  T::template PRE_MEM<PRE_PB, POST_PB>(address);
698  EmuTime time = T::getTimeFast(cc);
699  scheduler.schedule(time);
700  interface->writeMem(address, value, time);
701  T::template POST_MEM<POST_PB>(address);
702 }
703 template<class T> template<bool PRE_PB, bool POST_PB>
705  unsigned address, byte value, unsigned cc)
706 {
707  byte* line = writeCacheLine[address >> CacheLine::BITS];
708  if (likely(line != nullptr)) {
709  // cached, fast path
710  T::template PRE_MEM<PRE_PB, POST_PB>(address);
711  T::template POST_MEM< POST_PB>(address);
712  line[address] = value;
713  } else {
714  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
715  }
716 }
717 template<class T> template<bool PRE_PB, bool POST_PB>
719  unsigned address, byte value, unsigned cc)
720 {
721  static const bool PRE = T::template Normalize<PRE_PB >::value;
722  static const bool POST = T::template Normalize<POST_PB>::value;
723  WRMEM_impl2<PRE, POST>(address, value, cc);
724 }
725 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
726  unsigned address, byte value, unsigned cc)
727 {
728  WRMEM_impl<true, true>(address, value, cc);
729 }
730 
731 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
732  unsigned address, unsigned value, unsigned cc)
733 {
734  WRMEM_impl<true, false>( address, value & 255, cc);
735  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
736 }
737 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
738  unsigned address, unsigned value, unsigned cc)
739 {
740  byte* line = writeCacheLine[address >> CacheLine::BITS];
741  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
742  // fast path: cached and two bytes in same cache line
743  T::template PRE_WORD<true, true>(address);
744  T::template POST_WORD< true>(address);
745  Endian::write_UA_L16(&line[address], value);
746  } else {
747  // slow path, not inline
748  WR_WORD_slow(address, value, cc);
749  }
750 }
751 
752 // same as WR_WORD, but writes high byte first
753 template<class T> template<bool PRE_PB, bool POST_PB>
755  unsigned address, unsigned value, unsigned cc)
756 {
757  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
758  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
759 }
760 template<class T> template<bool PRE_PB, bool POST_PB>
762  unsigned address, unsigned value, unsigned cc)
763 {
764  byte* line = writeCacheLine[address >> CacheLine::BITS];
765  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
766  // fast path: cached and two bytes in same cache line
767  T::template PRE_WORD<PRE_PB, POST_PB>(address);
768  T::template POST_WORD< POST_PB>(address);
769  Endian::write_UA_L16(&line[address], value);
770  } else {
771  // slow path, not inline
772  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
773  }
774 }
775 template<class T> template<bool PRE_PB, bool POST_PB>
777  unsigned address, unsigned value, unsigned cc)
778 {
779  static const bool PRE = T::template Normalize<PRE_PB >::value;
780  static const bool POST = T::template Normalize<POST_PB>::value;
781  WR_WORD_rev2<PRE, POST>(address, value, cc);
782 }
783 
784 
785 // NMI interrupt
786 template<class T> inline void CPUCore<T>::nmi()
787 {
788  incR(1);
789  setHALT(false);
790  setIFF1(false);
791  PUSH<T::EE_NMI_1>(getPC());
792  setPC(0x0066);
793  T::add(T::CC_NMI);
794 }
795 
796 // IM0 interrupt
797 template<class T> inline void CPUCore<T>::irq0()
798 {
799  // TODO current implementation only works for 1-byte instructions
800  // ok for MSX
801  assert(interface->readIRQVector() == 0xFF);
802  incR(1);
803  setHALT(false);
804  setIFF1(false);
805  setIFF2(false);
806  PUSH<T::EE_IRQ0_1>(getPC());
807  setPC(0x0038);
808  T::setMemPtr(getPC());
809  T::add(T::CC_IRQ0);
810 }
811 
812 // IM1 interrupt
813 template<class T> inline void CPUCore<T>::irq1()
814 {
815  incR(1);
816  setHALT(false);
817  setIFF1(false);
818  setIFF2(false);
819  PUSH<T::EE_IRQ1_1>(getPC());
820  setPC(0x0038);
821  T::setMemPtr(getPC());
822  T::add(T::CC_IRQ1);
823 }
824 
825 // IM2 interrupt
826 template<class T> inline void CPUCore<T>::irq2()
827 {
828  incR(1);
829  setHALT(false);
830  setIFF1(false);
831  setIFF2(false);
832  PUSH<T::EE_IRQ2_1>(getPC());
833  unsigned x = interface->readIRQVector() | (getI() << 8);
834  setPC(RD_WORD(x, T::CC_IRQ2_2));
835  T::setMemPtr(getPC());
836  T::add(T::CC_IRQ2);
837 }
838 
839 template<class T>
840 void CPUCore<T>::executeInstructions()
841 {
842  assert(isNextAfterClear());
843 
844 #ifdef USE_COMPUTED_GOTO
845  // Addresses of all main-opcode routines,
846  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
847  static void* opcodeTable[256] = {
848  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
849  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
850  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
851  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
852  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
853  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
854  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
855  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
856  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
857  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
858  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
859  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
860  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
861  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
862  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
863  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
864  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
865  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
866  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
867  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
868  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
869  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
870  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
871  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
872  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
873  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
874  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
875  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
876  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
877  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
878  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
879  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
880  };
881 
882 // Check T::limitReached(). If it's OK to continue,
883 // fetch and execute next instruction.
884 #define NEXT \
885  T::add(c); \
886  T::R800Refresh(*this); \
887  if (likely(!T::limitReached())) { \
888  incR(1); \
889  unsigned address = getPC(); \
890  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
891  if (likely(line != nullptr)) { \
892  setPC(address + 1); \
893  T::template PRE_MEM<false, false>(address); \
894  T::template POST_MEM< false>(address); \
895  byte op = line[address]; \
896  goto *(opcodeTable[op]); \
897  } else { \
898  goto fetchSlow; \
899  } \
900  } \
901  return;
902 
903 // After some instructions we must always exit the CPU loop (ei, halt, retn)
904 #define NEXT_STOP \
905  T::add(c); \
906  T::R800Refresh(*this); \
907  assert(T::limitReached()); \
908  return;
909 
910 #define NEXT_EI \
911  T::add(c); \
912  /* !! NO T::R800Refresh(*this); !! */ \
913  assert(T::limitReached()); \
914  return;
915 
916 // Define a label (instead of case in a switch statement)
917 #define CASE(X) op##X:
918 
919 #else // USE_COMPUTED_GOTO
920 
921 #define NEXT \
922  T::add(c); \
923  T::R800Refresh(*this); \
924  if (likely(!T::limitReached())) { \
925  goto start; \
926  } \
927  return;
928 
929 #define NEXT_STOP \
930  T::add(c); \
931  T::R800Refresh(*this); \
932  assert(T::limitReached()); \
933  return;
934 
935 #define NEXT_EI \
936  T::add(c); \
937  /* !! NO T::R800Refresh(*this); !! */ \
938  assert(T::limitReached()); \
939  return;
940 
941 #define CASE(X) case 0x##X:
942 
943 #endif // USE_COMPUTED_GOTO
944 
945 #ifndef USE_COMPUTED_GOTO
946 start:
947 #endif
948  unsigned ixy; // for dd_cb/fd_cb
949  byte opcodeMain = RDMEM_OPCODE(T::CC_MAIN);
950  incR(1);
951 #ifdef USE_COMPUTED_GOTO
952  goto *(opcodeTable[opcodeMain]);
953 
954 fetchSlow: {
955  unsigned address = getPC();
956  setPC(address + 1);
957  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
958  goto *(opcodeTable[opcodeSlow]);
959 }
960 #endif
961 
962 #ifndef USE_COMPUTED_GOTO
963 switchopcode:
964  switch (opcodeMain) {
965 CASE(40) // ld b,b
966 CASE(49) // ld c,c
967 CASE(52) // ld d,d
968 CASE(5B) // ld e,e
969 CASE(64) // ld h,h
970 CASE(6D) // ld l,l
971 CASE(7F) // ld a,a
972 #endif
973 CASE(00) { int c = nop(); NEXT; }
974 CASE(07) { int c = rlca(); NEXT; }
975 CASE(0F) { int c = rrca(); NEXT; }
976 CASE(17) { int c = rla(); NEXT; }
977 CASE(1F) { int c = rra(); NEXT; }
978 CASE(08) { int c = ex_af_af(); NEXT; }
979 CASE(27) { int c = daa(); NEXT; }
980 CASE(2F) { int c = cpl(); NEXT; }
981 CASE(37) { int c = scf(); NEXT; }
982 CASE(3F) { int c = ccf(); NEXT; }
983 CASE(20) { int c = jr(CondNZ()); NEXT; }
984 CASE(28) { int c = jr(CondZ ()); NEXT; }
985 CASE(30) { int c = jr(CondNC()); NEXT; }
986 CASE(38) { int c = jr(CondC ()); NEXT; }
987 CASE(18) { int c = jr(CondTrue()); NEXT; }
988 CASE(10) { int c = djnz(); NEXT; }
989 CASE(32) { int c = ld_xbyte_a(); NEXT; }
990 CASE(3A) { int c = ld_a_xbyte(); NEXT; }
991 CASE(22) { int c = ld_xword_SS<HL,0>(); NEXT; }
992 CASE(2A) { int c = ld_SS_xword<HL,0>(); NEXT; }
993 CASE(02) { int c = ld_SS_a<BC>(); NEXT; }
994 CASE(12) { int c = ld_SS_a<DE>(); NEXT; }
995 CASE(1A) { int c = ld_a_SS<DE>(); NEXT; }
996 CASE(0A) { int c = ld_a_SS<BC>(); NEXT; }
997 CASE(03) { int c = inc_SS<BC,0>(); NEXT; }
998 CASE(13) { int c = inc_SS<DE,0>(); NEXT; }
999 CASE(23) { int c = inc_SS<HL,0>(); NEXT; }
1000 CASE(33) { int c = inc_SS<SP,0>(); NEXT; }
1001 CASE(0B) { int c = dec_SS<BC,0>(); NEXT; }
1002 CASE(1B) { int c = dec_SS<DE,0>(); NEXT; }
1003 CASE(2B) { int c = dec_SS<HL,0>(); NEXT; }
1004 CASE(3B) { int c = dec_SS<SP,0>(); NEXT; }
1005 CASE(09) { int c = add_SS_TT<HL,BC,0>(); NEXT; }
1006 CASE(19) { int c = add_SS_TT<HL,DE,0>(); NEXT; }
1007 CASE(29) { int c = add_SS_SS<HL ,0>(); NEXT; }
1008 CASE(39) { int c = add_SS_TT<HL,SP,0>(); NEXT; }
1009 CASE(01) { int c = ld_SS_word<BC,0>(); NEXT; }
1010 CASE(11) { int c = ld_SS_word<DE,0>(); NEXT; }
1011 CASE(21) { int c = ld_SS_word<HL,0>(); NEXT; }
1012 CASE(31) { int c = ld_SS_word<SP,0>(); NEXT; }
1013 CASE(04) { int c = inc_R<B,0>(); NEXT; }
1014 CASE(0C) { int c = inc_R<C,0>(); NEXT; }
1015 CASE(14) { int c = inc_R<D,0>(); NEXT; }
1016 CASE(1C) { int c = inc_R<E,0>(); NEXT; }
1017 CASE(24) { int c = inc_R<H,0>(); NEXT; }
1018 CASE(2C) { int c = inc_R<L,0>(); NEXT; }
1019 CASE(3C) { int c = inc_R<A,0>(); NEXT; }
1020 CASE(34) { int c = inc_xhl(); NEXT; }
1021 CASE(05) { int c = dec_R<B,0>(); NEXT; }
1022 CASE(0D) { int c = dec_R<C,0>(); NEXT; }
1023 CASE(15) { int c = dec_R<D,0>(); NEXT; }
1024 CASE(1D) { int c = dec_R<E,0>(); NEXT; }
1025 CASE(25) { int c = dec_R<H,0>(); NEXT; }
1026 CASE(2D) { int c = dec_R<L,0>(); NEXT; }
1027 CASE(3D) { int c = dec_R<A,0>(); NEXT; }
1028 CASE(35) { int c = dec_xhl(); NEXT; }
1029 CASE(06) { int c = ld_R_byte<B,0>(); NEXT; }
1030 CASE(0E) { int c = ld_R_byte<C,0>(); NEXT; }
1031 CASE(16) { int c = ld_R_byte<D,0>(); NEXT; }
1032 CASE(1E) { int c = ld_R_byte<E,0>(); NEXT; }
1033 CASE(26) { int c = ld_R_byte<H,0>(); NEXT; }
1034 CASE(2E) { int c = ld_R_byte<L,0>(); NEXT; }
1035 CASE(3E) { int c = ld_R_byte<A,0>(); NEXT; }
1036 CASE(36) { int c = ld_xhl_byte(); NEXT; }
1037 
1038 CASE(41) { int c = ld_R_R<B,C,0>(); NEXT; }
1039 CASE(42) { int c = ld_R_R<B,D,0>(); NEXT; }
1040 CASE(43) { int c = ld_R_R<B,E,0>(); NEXT; }
1041 CASE(44) { int c = ld_R_R<B,H,0>(); NEXT; }
1042 CASE(45) { int c = ld_R_R<B,L,0>(); NEXT; }
1043 CASE(47) { int c = ld_R_R<B,A,0>(); NEXT; }
1044 CASE(48) { int c = ld_R_R<C,B,0>(); NEXT; }
1045 CASE(4A) { int c = ld_R_R<C,D,0>(); NEXT; }
1046 CASE(4B) { int c = ld_R_R<C,E,0>(); NEXT; }
1047 CASE(4C) { int c = ld_R_R<C,H,0>(); NEXT; }
1048 CASE(4D) { int c = ld_R_R<C,L,0>(); NEXT; }
1049 CASE(4F) { int c = ld_R_R<C,A,0>(); NEXT; }
1050 CASE(50) { int c = ld_R_R<D,B,0>(); NEXT; }
1051 CASE(51) { int c = ld_R_R<D,C,0>(); NEXT; }
1052 CASE(53) { int c = ld_R_R<D,E,0>(); NEXT; }
1053 CASE(54) { int c = ld_R_R<D,H,0>(); NEXT; }
1054 CASE(55) { int c = ld_R_R<D,L,0>(); NEXT; }
1055 CASE(57) { int c = ld_R_R<D,A,0>(); NEXT; }
1056 CASE(58) { int c = ld_R_R<E,B,0>(); NEXT; }
1057 CASE(59) { int c = ld_R_R<E,C,0>(); NEXT; }
1058 CASE(5A) { int c = ld_R_R<E,D,0>(); NEXT; }
1059 CASE(5C) { int c = ld_R_R<E,H,0>(); NEXT; }
1060 CASE(5D) { int c = ld_R_R<E,L,0>(); NEXT; }
1061 CASE(5F) { int c = ld_R_R<E,A,0>(); NEXT; }
1062 CASE(60) { int c = ld_R_R<H,B,0>(); NEXT; }
1063 CASE(61) { int c = ld_R_R<H,C,0>(); NEXT; }
1064 CASE(62) { int c = ld_R_R<H,D,0>(); NEXT; }
1065 CASE(63) { int c = ld_R_R<H,E,0>(); NEXT; }
1066 CASE(65) { int c = ld_R_R<H,L,0>(); NEXT; }
1067 CASE(67) { int c = ld_R_R<H,A,0>(); NEXT; }
1068 CASE(68) { int c = ld_R_R<L,B,0>(); NEXT; }
1069 CASE(69) { int c = ld_R_R<L,C,0>(); NEXT; }
1070 CASE(6A) { int c = ld_R_R<L,D,0>(); NEXT; }
1071 CASE(6B) { int c = ld_R_R<L,E,0>(); NEXT; }
1072 CASE(6C) { int c = ld_R_R<L,H,0>(); NEXT; }
1073 CASE(6F) { int c = ld_R_R<L,A,0>(); NEXT; }
1074 CASE(78) { int c = ld_R_R<A,B,0>(); NEXT; }
1075 CASE(79) { int c = ld_R_R<A,C,0>(); NEXT; }
1076 CASE(7A) { int c = ld_R_R<A,D,0>(); NEXT; }
1077 CASE(7B) { int c = ld_R_R<A,E,0>(); NEXT; }
1078 CASE(7C) { int c = ld_R_R<A,H,0>(); NEXT; }
1079 CASE(7D) { int c = ld_R_R<A,L,0>(); NEXT; }
1080 CASE(70) { int c = ld_xhl_R<B>(); NEXT; }
1081 CASE(71) { int c = ld_xhl_R<C>(); NEXT; }
1082 CASE(72) { int c = ld_xhl_R<D>(); NEXT; }
1083 CASE(73) { int c = ld_xhl_R<E>(); NEXT; }
1084 CASE(74) { int c = ld_xhl_R<H>(); NEXT; }
1085 CASE(75) { int c = ld_xhl_R<L>(); NEXT; }
1086 CASE(77) { int c = ld_xhl_R<A>(); NEXT; }
1087 CASE(46) { int c = ld_R_xhl<B>(); NEXT; }
1088 CASE(4E) { int c = ld_R_xhl<C>(); NEXT; }
1089 CASE(56) { int c = ld_R_xhl<D>(); NEXT; }
1090 CASE(5E) { int c = ld_R_xhl<E>(); NEXT; }
1091 CASE(66) { int c = ld_R_xhl<H>(); NEXT; }
1092 CASE(6E) { int c = ld_R_xhl<L>(); NEXT; }
1093 CASE(7E) { int c = ld_R_xhl<A>(); NEXT; }
1094 CASE(76) { int c = halt(); NEXT_STOP; }
1095 
1096 CASE(80) { int c = add_a_R<B,0>(); NEXT; }
1097 CASE(81) { int c = add_a_R<C,0>(); NEXT; }
1098 CASE(82) { int c = add_a_R<D,0>(); NEXT; }
1099 CASE(83) { int c = add_a_R<E,0>(); NEXT; }
1100 CASE(84) { int c = add_a_R<H,0>(); NEXT; }
1101 CASE(85) { int c = add_a_R<L,0>(); NEXT; }
1102 CASE(86) { int c = add_a_xhl(); NEXT; }
1103 CASE(87) { int c = add_a_a(); NEXT; }
1104 CASE(88) { int c = adc_a_R<B,0>(); NEXT; }
1105 CASE(89) { int c = adc_a_R<C,0>(); NEXT; }
1106 CASE(8A) { int c = adc_a_R<D,0>(); NEXT; }
1107 CASE(8B) { int c = adc_a_R<E,0>(); NEXT; }
1108 CASE(8C) { int c = adc_a_R<H,0>(); NEXT; }
1109 CASE(8D) { int c = adc_a_R<L,0>(); NEXT; }
1110 CASE(8E) { int c = adc_a_xhl(); NEXT; }
1111 CASE(8F) { int c = adc_a_a(); NEXT; }
1112 CASE(90) { int c = sub_R<B,0>(); NEXT; }
1113 CASE(91) { int c = sub_R<C,0>(); NEXT; }
1114 CASE(92) { int c = sub_R<D,0>(); NEXT; }
1115 CASE(93) { int c = sub_R<E,0>(); NEXT; }
1116 CASE(94) { int c = sub_R<H,0>(); NEXT; }
1117 CASE(95) { int c = sub_R<L,0>(); NEXT; }
1118 CASE(96) { int c = sub_xhl(); NEXT; }
1119 CASE(97) { int c = sub_a(); NEXT; }
1120 CASE(98) { int c = sbc_a_R<B,0>(); NEXT; }
1121 CASE(99) { int c = sbc_a_R<C,0>(); NEXT; }
1122 CASE(9A) { int c = sbc_a_R<D,0>(); NEXT; }
1123 CASE(9B) { int c = sbc_a_R<E,0>(); NEXT; }
1124 CASE(9C) { int c = sbc_a_R<H,0>(); NEXT; }
1125 CASE(9D) { int c = sbc_a_R<L,0>(); NEXT; }
1126 CASE(9E) { int c = sbc_a_xhl(); NEXT; }
1127 CASE(9F) { int c = sbc_a_a(); NEXT; }
1128 CASE(A0) { int c = and_R<B,0>(); NEXT; }
1129 CASE(A1) { int c = and_R<C,0>(); NEXT; }
1130 CASE(A2) { int c = and_R<D,0>(); NEXT; }
1131 CASE(A3) { int c = and_R<E,0>(); NEXT; }
1132 CASE(A4) { int c = and_R<H,0>(); NEXT; }
1133 CASE(A5) { int c = and_R<L,0>(); NEXT; }
1134 CASE(A6) { int c = and_xhl(); NEXT; }
1135 CASE(A7) { int c = and_a(); NEXT; }
1136 CASE(A8) { int c = xor_R<B,0>(); NEXT; }
1137 CASE(A9) { int c = xor_R<C,0>(); NEXT; }
1138 CASE(AA) { int c = xor_R<D,0>(); NEXT; }
1139 CASE(AB) { int c = xor_R<E,0>(); NEXT; }
1140 CASE(AC) { int c = xor_R<H,0>(); NEXT; }
1141 CASE(AD) { int c = xor_R<L,0>(); NEXT; }
1142 CASE(AE) { int c = xor_xhl(); NEXT; }
1143 CASE(AF) { int c = xor_a(); NEXT; }
1144 CASE(B0) { int c = or_R<B,0>(); NEXT; }
1145 CASE(B1) { int c = or_R<C,0>(); NEXT; }
1146 CASE(B2) { int c = or_R<D,0>(); NEXT; }
1147 CASE(B3) { int c = or_R<E,0>(); NEXT; }
1148 CASE(B4) { int c = or_R<H,0>(); NEXT; }
1149 CASE(B5) { int c = or_R<L,0>(); NEXT; }
1150 CASE(B6) { int c = or_xhl(); NEXT; }
1151 CASE(B7) { int c = or_a(); NEXT; }
1152 CASE(B8) { int c = cp_R<B,0>(); NEXT; }
1153 CASE(B9) { int c = cp_R<C,0>(); NEXT; }
1154 CASE(BA) { int c = cp_R<D,0>(); NEXT; }
1155 CASE(BB) { int c = cp_R<E,0>(); NEXT; }
1156 CASE(BC) { int c = cp_R<H,0>(); NEXT; }
1157 CASE(BD) { int c = cp_R<L,0>(); NEXT; }
1158 CASE(BE) { int c = cp_xhl(); NEXT; }
1159 CASE(BF) { int c = cp_a(); NEXT; }
1160 
1161 CASE(D3) { int c = out_byte_a(); NEXT; }
1162 CASE(DB) { int c = in_a_byte(); NEXT; }
1163 CASE(D9) { int c = exx(); NEXT; }
1164 CASE(E3) { int c = ex_xsp_SS<HL,0>(); NEXT; }
1165 CASE(EB) { int c = ex_de_hl(); NEXT; }
1166 CASE(E9) { int c = jp_SS<HL,0>(); NEXT; }
1167 CASE(F9) { int c = ld_sp_SS<HL,0>(); NEXT; }
1168 CASE(F3) { int c = di(); NEXT; }
1169 CASE(FB) { int c = ei(); NEXT_EI; }
1170 CASE(C6) { int c = add_a_byte(); NEXT; }
1171 CASE(CE) { int c = adc_a_byte(); NEXT; }
1172 CASE(D6) { int c = sub_byte(); NEXT; }
1173 CASE(DE) { int c = sbc_a_byte(); NEXT; }
1174 CASE(E6) { int c = and_byte(); NEXT; }
1175 CASE(EE) { int c = xor_byte(); NEXT; }
1176 CASE(F6) { int c = or_byte(); NEXT; }
1177 CASE(FE) { int c = cp_byte(); NEXT; }
1178 CASE(C0) { int c = ret(CondNZ()); NEXT; }
1179 CASE(C8) { int c = ret(CondZ ()); NEXT; }
1180 CASE(D0) { int c = ret(CondNC()); NEXT; }
1181 CASE(D8) { int c = ret(CondC ()); NEXT; }
1182 CASE(E0) { int c = ret(CondPO()); NEXT; }
1183 CASE(E8) { int c = ret(CondPE()); NEXT; }
1184 CASE(F0) { int c = ret(CondP ()); NEXT; }
1185 CASE(F8) { int c = ret(CondM ()); NEXT; }
1186 CASE(C9) { int c = ret(); NEXT; }
1187 CASE(C2) { int c = jp(CondNZ()); NEXT; }
1188 CASE(CA) { int c = jp(CondZ ()); NEXT; }
1189 CASE(D2) { int c = jp(CondNC()); NEXT; }
1190 CASE(DA) { int c = jp(CondC ()); NEXT; }
1191 CASE(E2) { int c = jp(CondPO()); NEXT; }
1192 CASE(EA) { int c = jp(CondPE()); NEXT; }
1193 CASE(F2) { int c = jp(CondP ()); NEXT; }
1194 CASE(FA) { int c = jp(CondM ()); NEXT; }
1195 CASE(C3) { int c = jp(CondTrue()); NEXT; }
1196 CASE(C4) { int c = call(CondNZ()); NEXT; }
1197 CASE(CC) { int c = call(CondZ ()); NEXT; }
1198 CASE(D4) { int c = call(CondNC()); NEXT; }
1199 CASE(DC) { int c = call(CondC ()); NEXT; }
1200 CASE(E4) { int c = call(CondPO()); NEXT; }
1201 CASE(EC) { int c = call(CondPE()); NEXT; }
1202 CASE(F4) { int c = call(CondP ()); NEXT; }
1203 CASE(FC) { int c = call(CondM ()); NEXT; }
1204 CASE(CD) { int c = call(CondTrue()); NEXT; }
1205 CASE(C1) { int c = pop_SS <BC,0>(); NEXT; }
1206 CASE(D1) { int c = pop_SS <DE,0>(); NEXT; }
1207 CASE(E1) { int c = pop_SS <HL,0>(); NEXT; }
1208 CASE(F1) { int c = pop_SS <AF,0>(); NEXT; }
1209 CASE(C5) { int c = push_SS<BC,0>(); NEXT; }
1210 CASE(D5) { int c = push_SS<DE,0>(); NEXT; }
1211 CASE(E5) { int c = push_SS<HL,0>(); NEXT; }
1212 CASE(F5) { int c = push_SS<AF,0>(); NEXT; }
1213 CASE(C7) { int c = rst<0x00>(); NEXT; }
1214 CASE(CF) { int c = rst<0x08>(); NEXT; }
1215 CASE(D7) { int c = rst<0x10>(); NEXT; }
1216 CASE(DF) { int c = rst<0x18>(); NEXT; }
1217 CASE(E7) { int c = rst<0x20>(); NEXT; }
1218 CASE(EF) { int c = rst<0x28>(); NEXT; }
1219 CASE(F7) { int c = rst<0x30>(); NEXT; }
1220 CASE(FF) { int c = rst<0x38>(); NEXT; }
1221 CASE(CB) {
1222  byte cb_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1223  incR(1);
1224  switch (cb_opcode) {
1225  case 0x00: { int c = rlc_R<B>(); NEXT; }
1226  case 0x01: { int c = rlc_R<C>(); NEXT; }
1227  case 0x02: { int c = rlc_R<D>(); NEXT; }
1228  case 0x03: { int c = rlc_R<E>(); NEXT; }
1229  case 0x04: { int c = rlc_R<H>(); NEXT; }
1230  case 0x05: { int c = rlc_R<L>(); NEXT; }
1231  case 0x07: { int c = rlc_R<A>(); NEXT; }
1232  case 0x06: { int c = rlc_xhl(); NEXT; }
1233  case 0x08: { int c = rrc_R<B>(); NEXT; }
1234  case 0x09: { int c = rrc_R<C>(); NEXT; }
1235  case 0x0a: { int c = rrc_R<D>(); NEXT; }
1236  case 0x0b: { int c = rrc_R<E>(); NEXT; }
1237  case 0x0c: { int c = rrc_R<H>(); NEXT; }
1238  case 0x0d: { int c = rrc_R<L>(); NEXT; }
1239  case 0x0f: { int c = rrc_R<A>(); NEXT; }
1240  case 0x0e: { int c = rrc_xhl(); NEXT; }
1241  case 0x10: { int c = rl_R<B>(); NEXT; }
1242  case 0x11: { int c = rl_R<C>(); NEXT; }
1243  case 0x12: { int c = rl_R<D>(); NEXT; }
1244  case 0x13: { int c = rl_R<E>(); NEXT; }
1245  case 0x14: { int c = rl_R<H>(); NEXT; }
1246  case 0x15: { int c = rl_R<L>(); NEXT; }
1247  case 0x17: { int c = rl_R<A>(); NEXT; }
1248  case 0x16: { int c = rl_xhl(); NEXT; }
1249  case 0x18: { int c = rr_R<B>(); NEXT; }
1250  case 0x19: { int c = rr_R<C>(); NEXT; }
1251  case 0x1a: { int c = rr_R<D>(); NEXT; }
1252  case 0x1b: { int c = rr_R<E>(); NEXT; }
1253  case 0x1c: { int c = rr_R<H>(); NEXT; }
1254  case 0x1d: { int c = rr_R<L>(); NEXT; }
1255  case 0x1f: { int c = rr_R<A>(); NEXT; }
1256  case 0x1e: { int c = rr_xhl(); NEXT; }
1257  case 0x20: { int c = sla_R<B>(); NEXT; }
1258  case 0x21: { int c = sla_R<C>(); NEXT; }
1259  case 0x22: { int c = sla_R<D>(); NEXT; }
1260  case 0x23: { int c = sla_R<E>(); NEXT; }
1261  case 0x24: { int c = sla_R<H>(); NEXT; }
1262  case 0x25: { int c = sla_R<L>(); NEXT; }
1263  case 0x27: { int c = sla_R<A>(); NEXT; }
1264  case 0x26: { int c = sla_xhl(); NEXT; }
1265  case 0x28: { int c = sra_R<B>(); NEXT; }
1266  case 0x29: { int c = sra_R<C>(); NEXT; }
1267  case 0x2a: { int c = sra_R<D>(); NEXT; }
1268  case 0x2b: { int c = sra_R<E>(); NEXT; }
1269  case 0x2c: { int c = sra_R<H>(); NEXT; }
1270  case 0x2d: { int c = sra_R<L>(); NEXT; }
1271  case 0x2f: { int c = sra_R<A>(); NEXT; }
1272  case 0x2e: { int c = sra_xhl(); NEXT; }
1273  case 0x30: { int c = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1274  case 0x31: { int c = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1275  case 0x32: { int c = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1276  case 0x33: { int c = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1277  case 0x34: { int c = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1278  case 0x35: { int c = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1279  case 0x37: { int c = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1280  case 0x36: { int c = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1281  case 0x38: { int c = srl_R<B>(); NEXT; }
1282  case 0x39: { int c = srl_R<C>(); NEXT; }
1283  case 0x3a: { int c = srl_R<D>(); NEXT; }
1284  case 0x3b: { int c = srl_R<E>(); NEXT; }
1285  case 0x3c: { int c = srl_R<H>(); NEXT; }
1286  case 0x3d: { int c = srl_R<L>(); NEXT; }
1287  case 0x3f: { int c = srl_R<A>(); NEXT; }
1288  case 0x3e: { int c = srl_xhl(); NEXT; }
1289 
1290  case 0x40: { int c = bit_N_R<0,B>(); NEXT; }
1291  case 0x41: { int c = bit_N_R<0,C>(); NEXT; }
1292  case 0x42: { int c = bit_N_R<0,D>(); NEXT; }
1293  case 0x43: { int c = bit_N_R<0,E>(); NEXT; }
1294  case 0x44: { int c = bit_N_R<0,H>(); NEXT; }
1295  case 0x45: { int c = bit_N_R<0,L>(); NEXT; }
1296  case 0x47: { int c = bit_N_R<0,A>(); NEXT; }
1297  case 0x48: { int c = bit_N_R<1,B>(); NEXT; }
1298  case 0x49: { int c = bit_N_R<1,C>(); NEXT; }
1299  case 0x4a: { int c = bit_N_R<1,D>(); NEXT; }
1300  case 0x4b: { int c = bit_N_R<1,E>(); NEXT; }
1301  case 0x4c: { int c = bit_N_R<1,H>(); NEXT; }
1302  case 0x4d: { int c = bit_N_R<1,L>(); NEXT; }
1303  case 0x4f: { int c = bit_N_R<1,A>(); NEXT; }
1304  case 0x50: { int c = bit_N_R<2,B>(); NEXT; }
1305  case 0x51: { int c = bit_N_R<2,C>(); NEXT; }
1306  case 0x52: { int c = bit_N_R<2,D>(); NEXT; }
1307  case 0x53: { int c = bit_N_R<2,E>(); NEXT; }
1308  case 0x54: { int c = bit_N_R<2,H>(); NEXT; }
1309  case 0x55: { int c = bit_N_R<2,L>(); NEXT; }
1310  case 0x57: { int c = bit_N_R<2,A>(); NEXT; }
1311  case 0x58: { int c = bit_N_R<3,B>(); NEXT; }
1312  case 0x59: { int c = bit_N_R<3,C>(); NEXT; }
1313  case 0x5a: { int c = bit_N_R<3,D>(); NEXT; }
1314  case 0x5b: { int c = bit_N_R<3,E>(); NEXT; }
1315  case 0x5c: { int c = bit_N_R<3,H>(); NEXT; }
1316  case 0x5d: { int c = bit_N_R<3,L>(); NEXT; }
1317  case 0x5f: { int c = bit_N_R<3,A>(); NEXT; }
1318  case 0x60: { int c = bit_N_R<4,B>(); NEXT; }
1319  case 0x61: { int c = bit_N_R<4,C>(); NEXT; }
1320  case 0x62: { int c = bit_N_R<4,D>(); NEXT; }
1321  case 0x63: { int c = bit_N_R<4,E>(); NEXT; }
1322  case 0x64: { int c = bit_N_R<4,H>(); NEXT; }
1323  case 0x65: { int c = bit_N_R<4,L>(); NEXT; }
1324  case 0x67: { int c = bit_N_R<4,A>(); NEXT; }
1325  case 0x68: { int c = bit_N_R<5,B>(); NEXT; }
1326  case 0x69: { int c = bit_N_R<5,C>(); NEXT; }
1327  case 0x6a: { int c = bit_N_R<5,D>(); NEXT; }
1328  case 0x6b: { int c = bit_N_R<5,E>(); NEXT; }
1329  case 0x6c: { int c = bit_N_R<5,H>(); NEXT; }
1330  case 0x6d: { int c = bit_N_R<5,L>(); NEXT; }
1331  case 0x6f: { int c = bit_N_R<5,A>(); NEXT; }
1332  case 0x70: { int c = bit_N_R<6,B>(); NEXT; }
1333  case 0x71: { int c = bit_N_R<6,C>(); NEXT; }
1334  case 0x72: { int c = bit_N_R<6,D>(); NEXT; }
1335  case 0x73: { int c = bit_N_R<6,E>(); NEXT; }
1336  case 0x74: { int c = bit_N_R<6,H>(); NEXT; }
1337  case 0x75: { int c = bit_N_R<6,L>(); NEXT; }
1338  case 0x77: { int c = bit_N_R<6,A>(); NEXT; }
1339  case 0x78: { int c = bit_N_R<7,B>(); NEXT; }
1340  case 0x79: { int c = bit_N_R<7,C>(); NEXT; }
1341  case 0x7a: { int c = bit_N_R<7,D>(); NEXT; }
1342  case 0x7b: { int c = bit_N_R<7,E>(); NEXT; }
1343  case 0x7c: { int c = bit_N_R<7,H>(); NEXT; }
1344  case 0x7d: { int c = bit_N_R<7,L>(); NEXT; }
1345  case 0x7f: { int c = bit_N_R<7,A>(); NEXT; }
1346  case 0x46: { int c = bit_N_xhl<0>(); NEXT; }
1347  case 0x4e: { int c = bit_N_xhl<1>(); NEXT; }
1348  case 0x56: { int c = bit_N_xhl<2>(); NEXT; }
1349  case 0x5e: { int c = bit_N_xhl<3>(); NEXT; }
1350  case 0x66: { int c = bit_N_xhl<4>(); NEXT; }
1351  case 0x6e: { int c = bit_N_xhl<5>(); NEXT; }
1352  case 0x76: { int c = bit_N_xhl<6>(); NEXT; }
1353  case 0x7e: { int c = bit_N_xhl<7>(); NEXT; }
1354 
1355  case 0x80: { int c = res_N_R<0,B>(); NEXT; }
1356  case 0x81: { int c = res_N_R<0,C>(); NEXT; }
1357  case 0x82: { int c = res_N_R<0,D>(); NEXT; }
1358  case 0x83: { int c = res_N_R<0,E>(); NEXT; }
1359  case 0x84: { int c = res_N_R<0,H>(); NEXT; }
1360  case 0x85: { int c = res_N_R<0,L>(); NEXT; }
1361  case 0x87: { int c = res_N_R<0,A>(); NEXT; }
1362  case 0x88: { int c = res_N_R<1,B>(); NEXT; }
1363  case 0x89: { int c = res_N_R<1,C>(); NEXT; }
1364  case 0x8a: { int c = res_N_R<1,D>(); NEXT; }
1365  case 0x8b: { int c = res_N_R<1,E>(); NEXT; }
1366  case 0x8c: { int c = res_N_R<1,H>(); NEXT; }
1367  case 0x8d: { int c = res_N_R<1,L>(); NEXT; }
1368  case 0x8f: { int c = res_N_R<1,A>(); NEXT; }
1369  case 0x90: { int c = res_N_R<2,B>(); NEXT; }
1370  case 0x91: { int c = res_N_R<2,C>(); NEXT; }
1371  case 0x92: { int c = res_N_R<2,D>(); NEXT; }
1372  case 0x93: { int c = res_N_R<2,E>(); NEXT; }
1373  case 0x94: { int c = res_N_R<2,H>(); NEXT; }
1374  case 0x95: { int c = res_N_R<2,L>(); NEXT; }
1375  case 0x97: { int c = res_N_R<2,A>(); NEXT; }
1376  case 0x98: { int c = res_N_R<3,B>(); NEXT; }
1377  case 0x99: { int c = res_N_R<3,C>(); NEXT; }
1378  case 0x9a: { int c = res_N_R<3,D>(); NEXT; }
1379  case 0x9b: { int c = res_N_R<3,E>(); NEXT; }
1380  case 0x9c: { int c = res_N_R<3,H>(); NEXT; }
1381  case 0x9d: { int c = res_N_R<3,L>(); NEXT; }
1382  case 0x9f: { int c = res_N_R<3,A>(); NEXT; }
1383  case 0xa0: { int c = res_N_R<4,B>(); NEXT; }
1384  case 0xa1: { int c = res_N_R<4,C>(); NEXT; }
1385  case 0xa2: { int c = res_N_R<4,D>(); NEXT; }
1386  case 0xa3: { int c = res_N_R<4,E>(); NEXT; }
1387  case 0xa4: { int c = res_N_R<4,H>(); NEXT; }
1388  case 0xa5: { int c = res_N_R<4,L>(); NEXT; }
1389  case 0xa7: { int c = res_N_R<4,A>(); NEXT; }
1390  case 0xa8: { int c = res_N_R<5,B>(); NEXT; }
1391  case 0xa9: { int c = res_N_R<5,C>(); NEXT; }
1392  case 0xaa: { int c = res_N_R<5,D>(); NEXT; }
1393  case 0xab: { int c = res_N_R<5,E>(); NEXT; }
1394  case 0xac: { int c = res_N_R<5,H>(); NEXT; }
1395  case 0xad: { int c = res_N_R<5,L>(); NEXT; }
1396  case 0xaf: { int c = res_N_R<5,A>(); NEXT; }
1397  case 0xb0: { int c = res_N_R<6,B>(); NEXT; }
1398  case 0xb1: { int c = res_N_R<6,C>(); NEXT; }
1399  case 0xb2: { int c = res_N_R<6,D>(); NEXT; }
1400  case 0xb3: { int c = res_N_R<6,E>(); NEXT; }
1401  case 0xb4: { int c = res_N_R<6,H>(); NEXT; }
1402  case 0xb5: { int c = res_N_R<6,L>(); NEXT; }
1403  case 0xb7: { int c = res_N_R<6,A>(); NEXT; }
1404  case 0xb8: { int c = res_N_R<7,B>(); NEXT; }
1405  case 0xb9: { int c = res_N_R<7,C>(); NEXT; }
1406  case 0xba: { int c = res_N_R<7,D>(); NEXT; }
1407  case 0xbb: { int c = res_N_R<7,E>(); NEXT; }
1408  case 0xbc: { int c = res_N_R<7,H>(); NEXT; }
1409  case 0xbd: { int c = res_N_R<7,L>(); NEXT; }
1410  case 0xbf: { int c = res_N_R<7,A>(); NEXT; }
1411  case 0x86: { int c = res_N_xhl<0>(); NEXT; }
1412  case 0x8e: { int c = res_N_xhl<1>(); NEXT; }
1413  case 0x96: { int c = res_N_xhl<2>(); NEXT; }
1414  case 0x9e: { int c = res_N_xhl<3>(); NEXT; }
1415  case 0xa6: { int c = res_N_xhl<4>(); NEXT; }
1416  case 0xae: { int c = res_N_xhl<5>(); NEXT; }
1417  case 0xb6: { int c = res_N_xhl<6>(); NEXT; }
1418  case 0xbe: { int c = res_N_xhl<7>(); NEXT; }
1419 
1420  case 0xc0: { int c = set_N_R<0,B>(); NEXT; }
1421  case 0xc1: { int c = set_N_R<0,C>(); NEXT; }
1422  case 0xc2: { int c = set_N_R<0,D>(); NEXT; }
1423  case 0xc3: { int c = set_N_R<0,E>(); NEXT; }
1424  case 0xc4: { int c = set_N_R<0,H>(); NEXT; }
1425  case 0xc5: { int c = set_N_R<0,L>(); NEXT; }
1426  case 0xc7: { int c = set_N_R<0,A>(); NEXT; }
1427  case 0xc8: { int c = set_N_R<1,B>(); NEXT; }
1428  case 0xc9: { int c = set_N_R<1,C>(); NEXT; }
1429  case 0xca: { int c = set_N_R<1,D>(); NEXT; }
1430  case 0xcb: { int c = set_N_R<1,E>(); NEXT; }
1431  case 0xcc: { int c = set_N_R<1,H>(); NEXT; }
1432  case 0xcd: { int c = set_N_R<1,L>(); NEXT; }
1433  case 0xcf: { int c = set_N_R<1,A>(); NEXT; }
1434  case 0xd0: { int c = set_N_R<2,B>(); NEXT; }
1435  case 0xd1: { int c = set_N_R<2,C>(); NEXT; }
1436  case 0xd2: { int c = set_N_R<2,D>(); NEXT; }
1437  case 0xd3: { int c = set_N_R<2,E>(); NEXT; }
1438  case 0xd4: { int c = set_N_R<2,H>(); NEXT; }
1439  case 0xd5: { int c = set_N_R<2,L>(); NEXT; }
1440  case 0xd7: { int c = set_N_R<2,A>(); NEXT; }
1441  case 0xd8: { int c = set_N_R<3,B>(); NEXT; }
1442  case 0xd9: { int c = set_N_R<3,C>(); NEXT; }
1443  case 0xda: { int c = set_N_R<3,D>(); NEXT; }
1444  case 0xdb: { int c = set_N_R<3,E>(); NEXT; }
1445  case 0xdc: { int c = set_N_R<3,H>(); NEXT; }
1446  case 0xdd: { int c = set_N_R<3,L>(); NEXT; }
1447  case 0xdf: { int c = set_N_R<3,A>(); NEXT; }
1448  case 0xe0: { int c = set_N_R<4,B>(); NEXT; }
1449  case 0xe1: { int c = set_N_R<4,C>(); NEXT; }
1450  case 0xe2: { int c = set_N_R<4,D>(); NEXT; }
1451  case 0xe3: { int c = set_N_R<4,E>(); NEXT; }
1452  case 0xe4: { int c = set_N_R<4,H>(); NEXT; }
1453  case 0xe5: { int c = set_N_R<4,L>(); NEXT; }
1454  case 0xe7: { int c = set_N_R<4,A>(); NEXT; }
1455  case 0xe8: { int c = set_N_R<5,B>(); NEXT; }
1456  case 0xe9: { int c = set_N_R<5,C>(); NEXT; }
1457  case 0xea: { int c = set_N_R<5,D>(); NEXT; }
1458  case 0xeb: { int c = set_N_R<5,E>(); NEXT; }
1459  case 0xec: { int c = set_N_R<5,H>(); NEXT; }
1460  case 0xed: { int c = set_N_R<5,L>(); NEXT; }
1461  case 0xef: { int c = set_N_R<5,A>(); NEXT; }
1462  case 0xf0: { int c = set_N_R<6,B>(); NEXT; }
1463  case 0xf1: { int c = set_N_R<6,C>(); NEXT; }
1464  case 0xf2: { int c = set_N_R<6,D>(); NEXT; }
1465  case 0xf3: { int c = set_N_R<6,E>(); NEXT; }
1466  case 0xf4: { int c = set_N_R<6,H>(); NEXT; }
1467  case 0xf5: { int c = set_N_R<6,L>(); NEXT; }
1468  case 0xf7: { int c = set_N_R<6,A>(); NEXT; }
1469  case 0xf8: { int c = set_N_R<7,B>(); NEXT; }
1470  case 0xf9: { int c = set_N_R<7,C>(); NEXT; }
1471  case 0xfa: { int c = set_N_R<7,D>(); NEXT; }
1472  case 0xfb: { int c = set_N_R<7,E>(); NEXT; }
1473  case 0xfc: { int c = set_N_R<7,H>(); NEXT; }
1474  case 0xfd: { int c = set_N_R<7,L>(); NEXT; }
1475  case 0xff: { int c = set_N_R<7,A>(); NEXT; }
1476  case 0xc6: { int c = set_N_xhl<0>(); NEXT; }
1477  case 0xce: { int c = set_N_xhl<1>(); NEXT; }
1478  case 0xd6: { int c = set_N_xhl<2>(); NEXT; }
1479  case 0xde: { int c = set_N_xhl<3>(); NEXT; }
1480  case 0xe6: { int c = set_N_xhl<4>(); NEXT; }
1481  case 0xee: { int c = set_N_xhl<5>(); NEXT; }
1482  case 0xf6: { int c = set_N_xhl<6>(); NEXT; }
1483  case 0xfe: { int c = set_N_xhl<7>(); NEXT; }
1484  default: UNREACHABLE; return;
1485  }
1486 }
1487 CASE(ED) {
1488  byte ed_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1489  incR(1);
1490  switch (ed_opcode) {
1491  case 0x00: case 0x01: case 0x02: case 0x03:
1492  case 0x04: case 0x05: case 0x06: case 0x07:
1493  case 0x08: case 0x09: case 0x0a: case 0x0b:
1494  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1495  case 0x10: case 0x11: case 0x12: case 0x13:
1496  case 0x14: case 0x15: case 0x16: case 0x17:
1497  case 0x18: case 0x19: case 0x1a: case 0x1b:
1498  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1499  case 0x20: case 0x21: case 0x22: case 0x23:
1500  case 0x24: case 0x25: case 0x26: case 0x27:
1501  case 0x28: case 0x29: case 0x2a: case 0x2b:
1502  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1503  case 0x30: case 0x31: case 0x32: case 0x33:
1504  case 0x34: case 0x35: case 0x36: case 0x37:
1505  case 0x38: case 0x39: case 0x3a: case 0x3b:
1506  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1507 
1508  case 0x77: case 0x7f:
1509 
1510  case 0x80: case 0x81: case 0x82: case 0x83:
1511  case 0x84: case 0x85: case 0x86: case 0x87:
1512  case 0x88: case 0x89: case 0x8a: case 0x8b:
1513  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1514  case 0x90: case 0x91: case 0x92: case 0x93:
1515  case 0x94: case 0x95: case 0x96: case 0x97:
1516  case 0x98: case 0x99: case 0x9a: case 0x9b:
1517  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1518  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1519  case 0xac: case 0xad: case 0xae: case 0xaf:
1520  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1521  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1522 
1523  case 0xc0: case 0xc2:
1524  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1525  case 0xc8: case 0xca: case 0xcb:
1526  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1527  case 0xd0: case 0xd2: case 0xd3:
1528  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1529  case 0xd8: case 0xda: case 0xdb:
1530  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1531  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1532  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1533  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1534  case 0xec: case 0xed: case 0xee: case 0xef:
1535  case 0xf0: case 0xf1: case 0xf2:
1536  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1537  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1538  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1539  { int c = nop(); NEXT; }
1540 
1541  case 0x40: { int c = in_R_c<B>(); NEXT; }
1542  case 0x48: { int c = in_R_c<C>(); NEXT; }
1543  case 0x50: { int c = in_R_c<D>(); NEXT; }
1544  case 0x58: { int c = in_R_c<E>(); NEXT; }
1545  case 0x60: { int c = in_R_c<H>(); NEXT; }
1546  case 0x68: { int c = in_R_c<L>(); NEXT; }
1547  case 0x70: { int c = in_R_c<DUMMY>(); NEXT; }
1548  case 0x78: { int c = in_R_c<A>(); NEXT; }
1549 
1550  case 0x41: { int c = out_c_R<B>(); NEXT; }
1551  case 0x49: { int c = out_c_R<C>(); NEXT; }
1552  case 0x51: { int c = out_c_R<D>(); NEXT; }
1553  case 0x59: { int c = out_c_R<E>(); NEXT; }
1554  case 0x61: { int c = out_c_R<H>(); NEXT; }
1555  case 0x69: { int c = out_c_R<L>(); NEXT; }
1556  case 0x71: { int c = out_c_0(); NEXT; }
1557  case 0x79: { int c = out_c_R<A>(); NEXT; }
1558 
1559  case 0x42: { int c = sbc_hl_SS<BC>(); NEXT; }
1560  case 0x52: { int c = sbc_hl_SS<DE>(); NEXT; }
1561  case 0x62: { int c = sbc_hl_hl (); NEXT; }
1562  case 0x72: { int c = sbc_hl_SS<SP>(); NEXT; }
1563 
1564  case 0x4a: { int c = adc_hl_SS<BC>(); NEXT; }
1565  case 0x5a: { int c = adc_hl_SS<DE>(); NEXT; }
1566  case 0x6a: { int c = adc_hl_hl (); NEXT; }
1567  case 0x7a: { int c = adc_hl_SS<SP>(); NEXT; }
1568 
1569  case 0x43: { int c = ld_xword_SS_ED<BC>(); NEXT; }
1570  case 0x53: { int c = ld_xword_SS_ED<DE>(); NEXT; }
1571  case 0x63: { int c = ld_xword_SS_ED<HL>(); NEXT; }
1572  case 0x73: { int c = ld_xword_SS_ED<SP>(); NEXT; }
1573 
1574  case 0x4b: { int c = ld_SS_xword_ED<BC>(); NEXT; }
1575  case 0x5b: { int c = ld_SS_xword_ED<DE>(); NEXT; }
1576  case 0x6b: { int c = ld_SS_xword_ED<HL>(); NEXT; }
1577  case 0x7b: { int c = ld_SS_xword_ED<SP>(); NEXT; }
1578 
1579  case 0x47: { int c = ld_i_a(); NEXT; }
1580  case 0x4f: { int c = ld_r_a(); NEXT; }
1581  case 0x57: { int c = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1582  case 0x5f: { int c = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1583 
1584  case 0x67: { int c = rrd(); NEXT; }
1585  case 0x6f: { int c = rld(); NEXT; }
1586 
1587  case 0x45: case 0x4d: case 0x55: case 0x5d:
1588  case 0x65: case 0x6d: case 0x75: case 0x7d:
1589  { int c = retn(); NEXT_STOP; }
1590  case 0x46: case 0x4e: case 0x66: case 0x6e:
1591  { int c = im_N<0>(); NEXT; }
1592  case 0x56: case 0x76:
1593  { int c = im_N<1>(); NEXT; }
1594  case 0x5e: case 0x7e:
1595  { int c = im_N<2>(); NEXT; }
1596  case 0x44: case 0x4c: case 0x54: case 0x5c:
1597  case 0x64: case 0x6c: case 0x74: case 0x7c:
1598  { int c = neg(); NEXT; }
1599 
1600  case 0xa0: { int c = ldi(); NEXT; }
1601  case 0xa1: { int c = cpi(); NEXT; }
1602  case 0xa2: { int c = ini(); NEXT; }
1603  case 0xa3: { int c = outi(); NEXT; }
1604  case 0xa8: { int c = ldd(); NEXT; }
1605  case 0xa9: { int c = cpd(); NEXT; }
1606  case 0xaa: { int c = ind(); NEXT; }
1607  case 0xab: { int c = outd(); NEXT; }
1608  case 0xb0: { int c = ldir(); NEXT; }
1609  case 0xb1: { int c = cpir(); NEXT; }
1610  case 0xb2: { int c = inir(); NEXT; }
1611  case 0xb3: { int c = otir(); NEXT; }
1612  case 0xb8: { int c = lddr(); NEXT; }
1613  case 0xb9: { int c = cpdr(); NEXT; }
1614  case 0xba: { int c = indr(); NEXT; }
1615  case 0xbb: { int c = otdr(); NEXT; }
1616 
1617  case 0xc1: { int c = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1618  case 0xc9: { int c = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1619  case 0xd1: { int c = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1620  case 0xd9: { int c = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1621  case 0xc3: { int c = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1622  case 0xf3: { int c = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1623  default: UNREACHABLE; return;
1624  }
1625 }
1626 opDD_2:
1627 CASE(DD) {
1628  byte opcodeDD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1629  incR(1);
1630  switch (opcodeDD) {
1631  case 0x00: // nop();
1632  case 0x01: // ld_bc_word();
1633  case 0x02: // ld_xbc_a();
1634  case 0x03: // inc_bc();
1635  case 0x04: // inc_b();
1636  case 0x05: // dec_b();
1637  case 0x06: // ld_b_byte();
1638  case 0x07: // rlca();
1639  case 0x08: // ex_af_af();
1640  case 0x0a: // ld_a_xbc();
1641  case 0x0b: // dec_bc();
1642  case 0x0c: // inc_c();
1643  case 0x0d: // dec_c();
1644  case 0x0e: // ld_c_byte();
1645  case 0x0f: // rrca();
1646  case 0x10: // djnz();
1647  case 0x11: // ld_de_word();
1648  case 0x12: // ld_xde_a();
1649  case 0x13: // inc_de();
1650  case 0x14: // inc_d();
1651  case 0x15: // dec_d();
1652  case 0x16: // ld_d_byte();
1653  case 0x17: // rla();
1654  case 0x18: // jr();
1655  case 0x1a: // ld_a_xde();
1656  case 0x1b: // dec_de();
1657  case 0x1c: // inc_e();
1658  case 0x1d: // dec_e();
1659  case 0x1e: // ld_e_byte();
1660  case 0x1f: // rra();
1661  case 0x20: // jr_nz();
1662  case 0x27: // daa();
1663  case 0x28: // jr_z();
1664  case 0x2f: // cpl();
1665  case 0x30: // jr_nc();
1666  case 0x31: // ld_sp_word();
1667  case 0x32: // ld_xbyte_a();
1668  case 0x33: // inc_sp();
1669  case 0x37: // scf();
1670  case 0x38: // jr_c();
1671  case 0x3a: // ld_a_xbyte();
1672  case 0x3b: // dec_sp();
1673  case 0x3c: // inc_a();
1674  case 0x3d: // dec_a();
1675  case 0x3e: // ld_a_byte();
1676  case 0x3f: // ccf();
1677 
1678  case 0x40: // ld_b_b();
1679  case 0x41: // ld_b_c();
1680  case 0x42: // ld_b_d();
1681  case 0x43: // ld_b_e();
1682  case 0x47: // ld_b_a();
1683  case 0x48: // ld_c_b();
1684  case 0x49: // ld_c_c();
1685  case 0x4a: // ld_c_d();
1686  case 0x4b: // ld_c_e();
1687  case 0x4f: // ld_c_a();
1688  case 0x50: // ld_d_b();
1689  case 0x51: // ld_d_c();
1690  case 0x52: // ld_d_d();
1691  case 0x53: // ld_d_e();
1692  case 0x57: // ld_d_a();
1693  case 0x58: // ld_e_b();
1694  case 0x59: // ld_e_c();
1695  case 0x5a: // ld_e_d();
1696  case 0x5b: // ld_e_e();
1697  case 0x5f: // ld_e_a();
1698  case 0x64: // ld_ixh_ixh(); == nop
1699  case 0x6d: // ld_ixl_ixl(); == nop
1700  case 0x76: // halt();
1701  case 0x78: // ld_a_b();
1702  case 0x79: // ld_a_c();
1703  case 0x7a: // ld_a_d();
1704  case 0x7b: // ld_a_e();
1705  case 0x7f: // ld_a_a();
1706 
1707  case 0x80: // add_a_b();
1708  case 0x81: // add_a_c();
1709  case 0x82: // add_a_d();
1710  case 0x83: // add_a_e();
1711  case 0x87: // add_a_a();
1712  case 0x88: // adc_a_b();
1713  case 0x89: // adc_a_c();
1714  case 0x8a: // adc_a_d();
1715  case 0x8b: // adc_a_e();
1716  case 0x8f: // adc_a_a();
1717  case 0x90: // sub_b();
1718  case 0x91: // sub_c();
1719  case 0x92: // sub_d();
1720  case 0x93: // sub_e();
1721  case 0x97: // sub_a();
1722  case 0x98: // sbc_a_b();
1723  case 0x99: // sbc_a_c();
1724  case 0x9a: // sbc_a_d();
1725  case 0x9b: // sbc_a_e();
1726  case 0x9f: // sbc_a_a();
1727  case 0xa0: // and_b();
1728  case 0xa1: // and_c();
1729  case 0xa2: // and_d();
1730  case 0xa3: // and_e();
1731  case 0xa7: // and_a();
1732  case 0xa8: // xor_b();
1733  case 0xa9: // xor_c();
1734  case 0xaa: // xor_d();
1735  case 0xab: // xor_e();
1736  case 0xaf: // xor_a();
1737  case 0xb0: // or_b();
1738  case 0xb1: // or_c();
1739  case 0xb2: // or_d();
1740  case 0xb3: // or_e();
1741  case 0xb7: // or_a();
1742  case 0xb8: // cp_b();
1743  case 0xb9: // cp_c();
1744  case 0xba: // cp_d();
1745  case 0xbb: // cp_e();
1746  case 0xbf: // cp_a();
1747 
1748  case 0xc0: // ret_nz();
1749  case 0xc1: // pop_bc();
1750  case 0xc2: // jp_nz();
1751  case 0xc3: // jp();
1752  case 0xc4: // call_nz();
1753  case 0xc5: // push_bc();
1754  case 0xc6: // add_a_byte();
1755  case 0xc7: // rst_00();
1756  case 0xc8: // ret_z();
1757  case 0xc9: // ret();
1758  case 0xca: // jp_z();
1759  case 0xcc: // call_z();
1760  case 0xcd: // call();
1761  case 0xce: // adc_a_byte();
1762  case 0xcf: // rst_08();
1763  case 0xd0: // ret_nc();
1764  case 0xd1: // pop_de();
1765  case 0xd2: // jp_nc();
1766  case 0xd3: // out_byte_a();
1767  case 0xd4: // call_nc();
1768  case 0xd5: // push_de();
1769  case 0xd6: // sub_byte();
1770  case 0xd7: // rst_10();
1771  case 0xd8: // ret_c();
1772  case 0xd9: // exx();
1773  case 0xda: // jp_c();
1774  case 0xdb: // in_a_byte();
1775  case 0xdc: // call_c();
1776  case 0xde: // sbc_a_byte();
1777  case 0xdf: // rst_18();
1778  case 0xe0: // ret_po();
1779  case 0xe2: // jp_po();
1780  case 0xe4: // call_po();
1781  case 0xe6: // and_byte();
1782  case 0xe7: // rst_20();
1783  case 0xe8: // ret_pe();
1784  case 0xea: // jp_pe();
1785  case 0xeb: // ex_de_hl();
1786  case 0xec: // call_pe();
1787  case 0xed: // ed();
1788  case 0xee: // xor_byte();
1789  case 0xef: // rst_28();
1790  case 0xf0: // ret_p();
1791  case 0xf1: // pop_af();
1792  case 0xf2: // jp_p();
1793  case 0xf3: // di();
1794  case 0xf4: // call_p();
1795  case 0xf5: // push_af();
1796  case 0xf6: // or_byte();
1797  case 0xf7: // rst_30();
1798  case 0xf8: // ret_m();
1799  case 0xfa: // jp_m();
1800  case 0xfb: // ei();
1801  case 0xfc: // call_m();
1802  case 0xfe: // cp_byte();
1803  case 0xff: // rst_38();
1804  if (T::isR800()) {
1805  int c = T::CC_DD + nop(); NEXT;
1806  } else {
1807  T::add(T::CC_DD);
1808  #ifdef USE_COMPUTED_GOTO
1809  goto *(opcodeTable[opcodeDD]);
1810  #else
1811  opcodeMain = opcodeDD;
1812  goto switchopcode;
1813  #endif
1814  }
1815 
1816  case 0x09: { int c = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1817  case 0x19: { int c = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1818  case 0x29: { int c = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1819  case 0x39: { int c = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1820  case 0x21: { int c = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1821  case 0x22: { int c = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1822  case 0x2a: { int c = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1823  case 0x23: { int c = inc_SS<IX,T::CC_DD>(); NEXT; }
1824  case 0x2b: { int c = dec_SS<IX,T::CC_DD>(); NEXT; }
1825  case 0x24: { int c = inc_R<IXH,T::CC_DD>(); NEXT; }
1826  case 0x2c: { int c = inc_R<IXL,T::CC_DD>(); NEXT; }
1827  case 0x25: { int c = dec_R<IXH,T::CC_DD>(); NEXT; }
1828  case 0x2d: { int c = dec_R<IXL,T::CC_DD>(); NEXT; }
1829  case 0x26: { int c = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1830  case 0x2e: { int c = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1831  case 0x34: { int c = inc_xix<IX>(); NEXT; }
1832  case 0x35: { int c = dec_xix<IX>(); NEXT; }
1833  case 0x36: { int c = ld_xix_byte<IX>(); NEXT; }
1834 
1835  case 0x44: { int c = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1836  case 0x45: { int c = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1837  case 0x4c: { int c = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1838  case 0x4d: { int c = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1839  case 0x54: { int c = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1840  case 0x55: { int c = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1841  case 0x5c: { int c = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1842  case 0x5d: { int c = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1843  case 0x7c: { int c = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1844  case 0x7d: { int c = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1845  case 0x60: { int c = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1846  case 0x61: { int c = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1847  case 0x62: { int c = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1848  case 0x63: { int c = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1849  case 0x65: { int c = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1850  case 0x67: { int c = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1851  case 0x68: { int c = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1852  case 0x69: { int c = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1853  case 0x6a: { int c = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1854  case 0x6b: { int c = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1855  case 0x6c: { int c = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1856  case 0x6f: { int c = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1857  case 0x70: { int c = ld_xix_R<IX,B>(); NEXT; }
1858  case 0x71: { int c = ld_xix_R<IX,C>(); NEXT; }
1859  case 0x72: { int c = ld_xix_R<IX,D>(); NEXT; }
1860  case 0x73: { int c = ld_xix_R<IX,E>(); NEXT; }
1861  case 0x74: { int c = ld_xix_R<IX,H>(); NEXT; }
1862  case 0x75: { int c = ld_xix_R<IX,L>(); NEXT; }
1863  case 0x77: { int c = ld_xix_R<IX,A>(); NEXT; }
1864  case 0x46: { int c = ld_R_xix<B,IX>(); NEXT; }
1865  case 0x4e: { int c = ld_R_xix<C,IX>(); NEXT; }
1866  case 0x56: { int c = ld_R_xix<D,IX>(); NEXT; }
1867  case 0x5e: { int c = ld_R_xix<E,IX>(); NEXT; }
1868  case 0x66: { int c = ld_R_xix<H,IX>(); NEXT; }
1869  case 0x6e: { int c = ld_R_xix<L,IX>(); NEXT; }
1870  case 0x7e: { int c = ld_R_xix<A,IX>(); NEXT; }
1871 
1872  case 0x84: { int c = add_a_R<IXH,T::CC_DD>(); NEXT; }
1873  case 0x85: { int c = add_a_R<IXL,T::CC_DD>(); NEXT; }
1874  case 0x86: { int c = add_a_xix<IX>(); NEXT; }
1875  case 0x8c: { int c = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1876  case 0x8d: { int c = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1877  case 0x8e: { int c = adc_a_xix<IX>(); NEXT; }
1878  case 0x94: { int c = sub_R<IXH,T::CC_DD>(); NEXT; }
1879  case 0x95: { int c = sub_R<IXL,T::CC_DD>(); NEXT; }
1880  case 0x96: { int c = sub_xix<IX>(); NEXT; }
1881  case 0x9c: { int c = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1882  case 0x9d: { int c = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1883  case 0x9e: { int c = sbc_a_xix<IX>(); NEXT; }
1884  case 0xa4: { int c = and_R<IXH,T::CC_DD>(); NEXT; }
1885  case 0xa5: { int c = and_R<IXL,T::CC_DD>(); NEXT; }
1886  case 0xa6: { int c = and_xix<IX>(); NEXT; }
1887  case 0xac: { int c = xor_R<IXH,T::CC_DD>(); NEXT; }
1888  case 0xad: { int c = xor_R<IXL,T::CC_DD>(); NEXT; }
1889  case 0xae: { int c = xor_xix<IX>(); NEXT; }
1890  case 0xb4: { int c = or_R<IXH,T::CC_DD>(); NEXT; }
1891  case 0xb5: { int c = or_R<IXL,T::CC_DD>(); NEXT; }
1892  case 0xb6: { int c = or_xix<IX>(); NEXT; }
1893  case 0xbc: { int c = cp_R<IXH,T::CC_DD>(); NEXT; }
1894  case 0xbd: { int c = cp_R<IXL,T::CC_DD>(); NEXT; }
1895  case 0xbe: { int c = cp_xix<IX>(); NEXT; }
1896 
1897  case 0xe1: { int c = pop_SS <IX,T::CC_DD>(); NEXT; }
1898  case 0xe5: { int c = push_SS<IX,T::CC_DD>(); NEXT; }
1899  case 0xe3: { int c = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1900  case 0xe9: { int c = jp_SS<IX,T::CC_DD>(); NEXT; }
1901  case 0xf9: { int c = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1902  case 0xcb: ixy = getIX(); goto xx_cb;
1903  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1904  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1905  default: UNREACHABLE; return;
1906  }
1907 }
1908 opFD_2:
1909 CASE(FD) {
1910  byte opcodeFD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1911  incR(1);
1912  switch (opcodeFD) {
1913  case 0x00: // nop();
1914  case 0x01: // ld_bc_word();
1915  case 0x02: // ld_xbc_a();
1916  case 0x03: // inc_bc();
1917  case 0x04: // inc_b();
1918  case 0x05: // dec_b();
1919  case 0x06: // ld_b_byte();
1920  case 0x07: // rlca();
1921  case 0x08: // ex_af_af();
1922  case 0x0a: // ld_a_xbc();
1923  case 0x0b: // dec_bc();
1924  case 0x0c: // inc_c();
1925  case 0x0d: // dec_c();
1926  case 0x0e: // ld_c_byte();
1927  case 0x0f: // rrca();
1928  case 0x10: // djnz();
1929  case 0x11: // ld_de_word();
1930  case 0x12: // ld_xde_a();
1931  case 0x13: // inc_de();
1932  case 0x14: // inc_d();
1933  case 0x15: // dec_d();
1934  case 0x16: // ld_d_byte();
1935  case 0x17: // rla();
1936  case 0x18: // jr();
1937  case 0x1a: // ld_a_xde();
1938  case 0x1b: // dec_de();
1939  case 0x1c: // inc_e();
1940  case 0x1d: // dec_e();
1941  case 0x1e: // ld_e_byte();
1942  case 0x1f: // rra();
1943  case 0x20: // jr_nz();
1944  case 0x27: // daa();
1945  case 0x28: // jr_z();
1946  case 0x2f: // cpl();
1947  case 0x30: // jr_nc();
1948  case 0x31: // ld_sp_word();
1949  case 0x32: // ld_xbyte_a();
1950  case 0x33: // inc_sp();
1951  case 0x37: // scf();
1952  case 0x38: // jr_c();
1953  case 0x3a: // ld_a_xbyte();
1954  case 0x3b: // dec_sp();
1955  case 0x3c: // inc_a();
1956  case 0x3d: // dec_a();
1957  case 0x3e: // ld_a_byte();
1958  case 0x3f: // ccf();
1959 
1960  case 0x40: // ld_b_b();
1961  case 0x41: // ld_b_c();
1962  case 0x42: // ld_b_d();
1963  case 0x43: // ld_b_e();
1964  case 0x47: // ld_b_a();
1965  case 0x48: // ld_c_b();
1966  case 0x49: // ld_c_c();
1967  case 0x4a: // ld_c_d();
1968  case 0x4b: // ld_c_e();
1969  case 0x4f: // ld_c_a();
1970  case 0x50: // ld_d_b();
1971  case 0x51: // ld_d_c();
1972  case 0x52: // ld_d_d();
1973  case 0x53: // ld_d_e();
1974  case 0x57: // ld_d_a();
1975  case 0x58: // ld_e_b();
1976  case 0x59: // ld_e_c();
1977  case 0x5a: // ld_e_d();
1978  case 0x5b: // ld_e_e();
1979  case 0x5f: // ld_e_a();
1980  case 0x64: // ld_ixh_ixh(); == nop
1981  case 0x6d: // ld_ixl_ixl(); == nop
1982  case 0x76: // halt();
1983  case 0x78: // ld_a_b();
1984  case 0x79: // ld_a_c();
1985  case 0x7a: // ld_a_d();
1986  case 0x7b: // ld_a_e();
1987  case 0x7f: // ld_a_a();
1988 
1989  case 0x80: // add_a_b();
1990  case 0x81: // add_a_c();
1991  case 0x82: // add_a_d();
1992  case 0x83: // add_a_e();
1993  case 0x87: // add_a_a();
1994  case 0x88: // adc_a_b();
1995  case 0x89: // adc_a_c();
1996  case 0x8a: // adc_a_d();
1997  case 0x8b: // adc_a_e();
1998  case 0x8f: // adc_a_a();
1999  case 0x90: // sub_b();
2000  case 0x91: // sub_c();
2001  case 0x92: // sub_d();
2002  case 0x93: // sub_e();
2003  case 0x97: // sub_a();
2004  case 0x98: // sbc_a_b();
2005  case 0x99: // sbc_a_c();
2006  case 0x9a: // sbc_a_d();
2007  case 0x9b: // sbc_a_e();
2008  case 0x9f: // sbc_a_a();
2009  case 0xa0: // and_b();
2010  case 0xa1: // and_c();
2011  case 0xa2: // and_d();
2012  case 0xa3: // and_e();
2013  case 0xa7: // and_a();
2014  case 0xa8: // xor_b();
2015  case 0xa9: // xor_c();
2016  case 0xaa: // xor_d();
2017  case 0xab: // xor_e();
2018  case 0xaf: // xor_a();
2019  case 0xb0: // or_b();
2020  case 0xb1: // or_c();
2021  case 0xb2: // or_d();
2022  case 0xb3: // or_e();
2023  case 0xb7: // or_a();
2024  case 0xb8: // cp_b();
2025  case 0xb9: // cp_c();
2026  case 0xba: // cp_d();
2027  case 0xbb: // cp_e();
2028  case 0xbf: // cp_a();
2029 
2030  case 0xc0: // ret_nz();
2031  case 0xc1: // pop_bc();
2032  case 0xc2: // jp_nz();
2033  case 0xc3: // jp();
2034  case 0xc4: // call_nz();
2035  case 0xc5: // push_bc();
2036  case 0xc6: // add_a_byte();
2037  case 0xc7: // rst_00();
2038  case 0xc8: // ret_z();
2039  case 0xc9: // ret();
2040  case 0xca: // jp_z();
2041  case 0xcc: // call_z();
2042  case 0xcd: // call();
2043  case 0xce: // adc_a_byte();
2044  case 0xcf: // rst_08();
2045  case 0xd0: // ret_nc();
2046  case 0xd1: // pop_de();
2047  case 0xd2: // jp_nc();
2048  case 0xd3: // out_byte_a();
2049  case 0xd4: // call_nc();
2050  case 0xd5: // push_de();
2051  case 0xd6: // sub_byte();
2052  case 0xd7: // rst_10();
2053  case 0xd8: // ret_c();
2054  case 0xd9: // exx();
2055  case 0xda: // jp_c();
2056  case 0xdb: // in_a_byte();
2057  case 0xdc: // call_c();
2058  case 0xde: // sbc_a_byte();
2059  case 0xdf: // rst_18();
2060  case 0xe0: // ret_po();
2061  case 0xe2: // jp_po();
2062  case 0xe4: // call_po();
2063  case 0xe6: // and_byte();
2064  case 0xe7: // rst_20();
2065  case 0xe8: // ret_pe();
2066  case 0xea: // jp_pe();
2067  case 0xeb: // ex_de_hl();
2068  case 0xec: // call_pe();
2069  case 0xed: // ed();
2070  case 0xee: // xor_byte();
2071  case 0xef: // rst_28();
2072  case 0xf0: // ret_p();
2073  case 0xf1: // pop_af();
2074  case 0xf2: // jp_p();
2075  case 0xf3: // di();
2076  case 0xf4: // call_p();
2077  case 0xf5: // push_af();
2078  case 0xf6: // or_byte();
2079  case 0xf7: // rst_30();
2080  case 0xf8: // ret_m();
2081  case 0xfa: // jp_m();
2082  case 0xfb: // ei();
2083  case 0xfc: // call_m();
2084  case 0xfe: // cp_byte();
2085  case 0xff: // rst_38();
2086  if (T::isR800()) {
2087  int c = T::CC_DD + nop(); NEXT;
2088  } else {
2089  T::add(T::CC_DD);
2090  #ifdef USE_COMPUTED_GOTO
2091  goto *(opcodeTable[opcodeFD]);
2092  #else
2093  opcodeMain = opcodeFD;
2094  goto switchopcode;
2095  #endif
2096  }
2097 
2098  case 0x09: { int c = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2099  case 0x19: { int c = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2100  case 0x29: { int c = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2101  case 0x39: { int c = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2102  case 0x21: { int c = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2103  case 0x22: { int c = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2104  case 0x2a: { int c = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2105  case 0x23: { int c = inc_SS<IY,T::CC_DD>(); NEXT; }
2106  case 0x2b: { int c = dec_SS<IY,T::CC_DD>(); NEXT; }
2107  case 0x24: { int c = inc_R<IYH,T::CC_DD>(); NEXT; }
2108  case 0x2c: { int c = inc_R<IYL,T::CC_DD>(); NEXT; }
2109  case 0x25: { int c = dec_R<IYH,T::CC_DD>(); NEXT; }
2110  case 0x2d: { int c = dec_R<IYL,T::CC_DD>(); NEXT; }
2111  case 0x26: { int c = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2112  case 0x2e: { int c = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2113  case 0x34: { int c = inc_xix<IY>(); NEXT; }
2114  case 0x35: { int c = dec_xix<IY>(); NEXT; }
2115  case 0x36: { int c = ld_xix_byte<IY>(); NEXT; }
2116 
2117  case 0x44: { int c = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2118  case 0x45: { int c = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2119  case 0x4c: { int c = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2120  case 0x4d: { int c = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2121  case 0x54: { int c = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2122  case 0x55: { int c = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2123  case 0x5c: { int c = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2124  case 0x5d: { int c = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2125  case 0x7c: { int c = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2126  case 0x7d: { int c = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2127  case 0x60: { int c = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2128  case 0x61: { int c = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2129  case 0x62: { int c = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2130  case 0x63: { int c = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2131  case 0x65: { int c = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2132  case 0x67: { int c = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2133  case 0x68: { int c = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2134  case 0x69: { int c = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2135  case 0x6a: { int c = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2136  case 0x6b: { int c = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2137  case 0x6c: { int c = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2138  case 0x6f: { int c = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2139  case 0x70: { int c = ld_xix_R<IY,B>(); NEXT; }
2140  case 0x71: { int c = ld_xix_R<IY,C>(); NEXT; }
2141  case 0x72: { int c = ld_xix_R<IY,D>(); NEXT; }
2142  case 0x73: { int c = ld_xix_R<IY,E>(); NEXT; }
2143  case 0x74: { int c = ld_xix_R<IY,H>(); NEXT; }
2144  case 0x75: { int c = ld_xix_R<IY,L>(); NEXT; }
2145  case 0x77: { int c = ld_xix_R<IY,A>(); NEXT; }
2146  case 0x46: { int c = ld_R_xix<B,IY>(); NEXT; }
2147  case 0x4e: { int c = ld_R_xix<C,IY>(); NEXT; }
2148  case 0x56: { int c = ld_R_xix<D,IY>(); NEXT; }
2149  case 0x5e: { int c = ld_R_xix<E,IY>(); NEXT; }
2150  case 0x66: { int c = ld_R_xix<H,IY>(); NEXT; }
2151  case 0x6e: { int c = ld_R_xix<L,IY>(); NEXT; }
2152  case 0x7e: { int c = ld_R_xix<A,IY>(); NEXT; }
2153 
2154  case 0x84: { int c = add_a_R<IYH,T::CC_DD>(); NEXT; }
2155  case 0x85: { int c = add_a_R<IYL,T::CC_DD>(); NEXT; }
2156  case 0x86: { int c = add_a_xix<IY>(); NEXT; }
2157  case 0x8c: { int c = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2158  case 0x8d: { int c = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2159  case 0x8e: { int c = adc_a_xix<IY>(); NEXT; }
2160  case 0x94: { int c = sub_R<IYH,T::CC_DD>(); NEXT; }
2161  case 0x95: { int c = sub_R<IYL,T::CC_DD>(); NEXT; }
2162  case 0x96: { int c = sub_xix<IY>(); NEXT; }
2163  case 0x9c: { int c = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2164  case 0x9d: { int c = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2165  case 0x9e: { int c = sbc_a_xix<IY>(); NEXT; }
2166  case 0xa4: { int c = and_R<IYH,T::CC_DD>(); NEXT; }
2167  case 0xa5: { int c = and_R<IYL,T::CC_DD>(); NEXT; }
2168  case 0xa6: { int c = and_xix<IY>(); NEXT; }
2169  case 0xac: { int c = xor_R<IYH,T::CC_DD>(); NEXT; }
2170  case 0xad: { int c = xor_R<IYL,T::CC_DD>(); NEXT; }
2171  case 0xae: { int c = xor_xix<IY>(); NEXT; }
2172  case 0xb4: { int c = or_R<IYH,T::CC_DD>(); NEXT; }
2173  case 0xb5: { int c = or_R<IYL,T::CC_DD>(); NEXT; }
2174  case 0xb6: { int c = or_xix<IY>(); NEXT; }
2175  case 0xbc: { int c = cp_R<IYH,T::CC_DD>(); NEXT; }
2176  case 0xbd: { int c = cp_R<IYL,T::CC_DD>(); NEXT; }
2177  case 0xbe: { int c = cp_xix<IY>(); NEXT; }
2178 
2179  case 0xe1: { int c = pop_SS <IY,T::CC_DD>(); NEXT; }
2180  case 0xe5: { int c = push_SS<IY,T::CC_DD>(); NEXT; }
2181  case 0xe3: { int c = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2182  case 0xe9: { int c = jp_SS<IY,T::CC_DD>(); NEXT; }
2183  case 0xf9: { int c = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2184  case 0xcb: ixy = getIY(); goto xx_cb;
2185  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2186  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2187  default: UNREACHABLE; return;
2188  }
2189 }
2190 #ifndef USE_COMPUTED_GOTO
2191  default: UNREACHABLE; return;
2192 }
2193 #endif
2194 
2195 xx_cb: {
2196  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_DD_CB);
2197  offset ofst = tmp & 0xFF;
2198  unsigned addr = (ixy + ofst) & 0xFFFF;
2199  byte xxcb_opcode = tmp >> 8;
2200  switch (xxcb_opcode) {
2201  case 0x00: { int c = rlc_xix_R<B>(addr); NEXT; }
2202  case 0x01: { int c = rlc_xix_R<C>(addr); NEXT; }
2203  case 0x02: { int c = rlc_xix_R<D>(addr); NEXT; }
2204  case 0x03: { int c = rlc_xix_R<E>(addr); NEXT; }
2205  case 0x04: { int c = rlc_xix_R<H>(addr); NEXT; }
2206  case 0x05: { int c = rlc_xix_R<L>(addr); NEXT; }
2207  case 0x06: { int c = rlc_xix_R<DUMMY>(addr); NEXT; }
2208  case 0x07: { int c = rlc_xix_R<A>(addr); NEXT; }
2209  case 0x08: { int c = rrc_xix_R<B>(addr); NEXT; }
2210  case 0x09: { int c = rrc_xix_R<C>(addr); NEXT; }
2211  case 0x0a: { int c = rrc_xix_R<D>(addr); NEXT; }
2212  case 0x0b: { int c = rrc_xix_R<E>(addr); NEXT; }
2213  case 0x0c: { int c = rrc_xix_R<H>(addr); NEXT; }
2214  case 0x0d: { int c = rrc_xix_R<L>(addr); NEXT; }
2215  case 0x0e: { int c = rrc_xix_R<DUMMY>(addr); NEXT; }
2216  case 0x0f: { int c = rrc_xix_R<A>(addr); NEXT; }
2217  case 0x10: { int c = rl_xix_R<B>(addr); NEXT; }
2218  case 0x11: { int c = rl_xix_R<C>(addr); NEXT; }
2219  case 0x12: { int c = rl_xix_R<D>(addr); NEXT; }
2220  case 0x13: { int c = rl_xix_R<E>(addr); NEXT; }
2221  case 0x14: { int c = rl_xix_R<H>(addr); NEXT; }
2222  case 0x15: { int c = rl_xix_R<L>(addr); NEXT; }
2223  case 0x16: { int c = rl_xix_R<DUMMY>(addr); NEXT; }
2224  case 0x17: { int c = rl_xix_R<A>(addr); NEXT; }
2225  case 0x18: { int c = rr_xix_R<B>(addr); NEXT; }
2226  case 0x19: { int c = rr_xix_R<C>(addr); NEXT; }
2227  case 0x1a: { int c = rr_xix_R<D>(addr); NEXT; }
2228  case 0x1b: { int c = rr_xix_R<E>(addr); NEXT; }
2229  case 0x1c: { int c = rr_xix_R<H>(addr); NEXT; }
2230  case 0x1d: { int c = rr_xix_R<L>(addr); NEXT; }
2231  case 0x1e: { int c = rr_xix_R<DUMMY>(addr); NEXT; }
2232  case 0x1f: { int c = rr_xix_R<A>(addr); NEXT; }
2233  case 0x20: { int c = sla_xix_R<B>(addr); NEXT; }
2234  case 0x21: { int c = sla_xix_R<C>(addr); NEXT; }
2235  case 0x22: { int c = sla_xix_R<D>(addr); NEXT; }
2236  case 0x23: { int c = sla_xix_R<E>(addr); NEXT; }
2237  case 0x24: { int c = sla_xix_R<H>(addr); NEXT; }
2238  case 0x25: { int c = sla_xix_R<L>(addr); NEXT; }
2239  case 0x26: { int c = sla_xix_R<DUMMY>(addr); NEXT; }
2240  case 0x27: { int c = sla_xix_R<A>(addr); NEXT; }
2241  case 0x28: { int c = sra_xix_R<B>(addr); NEXT; }
2242  case 0x29: { int c = sra_xix_R<C>(addr); NEXT; }
2243  case 0x2a: { int c = sra_xix_R<D>(addr); NEXT; }
2244  case 0x2b: { int c = sra_xix_R<E>(addr); NEXT; }
2245  case 0x2c: { int c = sra_xix_R<H>(addr); NEXT; }
2246  case 0x2d: { int c = sra_xix_R<L>(addr); NEXT; }
2247  case 0x2e: { int c = sra_xix_R<DUMMY>(addr); NEXT; }
2248  case 0x2f: { int c = sra_xix_R<A>(addr); NEXT; }
2249  case 0x30: { int c = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2250  case 0x31: { int c = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2251  case 0x32: { int c = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2252  case 0x33: { int c = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2253  case 0x34: { int c = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2254  case 0x35: { int c = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2255  case 0x36: { int c = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2256  case 0x37: { int c = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2257  case 0x38: { int c = srl_xix_R<B>(addr); NEXT; }
2258  case 0x39: { int c = srl_xix_R<C>(addr); NEXT; }
2259  case 0x3a: { int c = srl_xix_R<D>(addr); NEXT; }
2260  case 0x3b: { int c = srl_xix_R<E>(addr); NEXT; }
2261  case 0x3c: { int c = srl_xix_R<H>(addr); NEXT; }
2262  case 0x3d: { int c = srl_xix_R<L>(addr); NEXT; }
2263  case 0x3e: { int c = srl_xix_R<DUMMY>(addr); NEXT; }
2264  case 0x3f: { int c = srl_xix_R<A>(addr); NEXT; }
2265 
2266  case 0x40: case 0x41: case 0x42: case 0x43:
2267  case 0x44: case 0x45: case 0x46: case 0x47:
2268  { int c = bit_N_xix<0>(addr); NEXT; }
2269  case 0x48: case 0x49: case 0x4a: case 0x4b:
2270  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2271  { int c = bit_N_xix<1>(addr); NEXT; }
2272  case 0x50: case 0x51: case 0x52: case 0x53:
2273  case 0x54: case 0x55: case 0x56: case 0x57:
2274  { int c = bit_N_xix<2>(addr); NEXT; }
2275  case 0x58: case 0x59: case 0x5a: case 0x5b:
2276  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2277  { int c = bit_N_xix<3>(addr); NEXT; }
2278  case 0x60: case 0x61: case 0x62: case 0x63:
2279  case 0x64: case 0x65: case 0x66: case 0x67:
2280  { int c = bit_N_xix<4>(addr); NEXT; }
2281  case 0x68: case 0x69: case 0x6a: case 0x6b:
2282  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2283  { int c = bit_N_xix<5>(addr); NEXT; }
2284  case 0x70: case 0x71: case 0x72: case 0x73:
2285  case 0x74: case 0x75: case 0x76: case 0x77:
2286  { int c = bit_N_xix<6>(addr); NEXT; }
2287  case 0x78: case 0x79: case 0x7a: case 0x7b:
2288  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2289  { int c = bit_N_xix<7>(addr); NEXT; }
2290 
2291  case 0x80: { int c = res_N_xix_R<0,B>(addr); NEXT; }
2292  case 0x81: { int c = res_N_xix_R<0,C>(addr); NEXT; }
2293  case 0x82: { int c = res_N_xix_R<0,D>(addr); NEXT; }
2294  case 0x83: { int c = res_N_xix_R<0,E>(addr); NEXT; }
2295  case 0x84: { int c = res_N_xix_R<0,H>(addr); NEXT; }
2296  case 0x85: { int c = res_N_xix_R<0,L>(addr); NEXT; }
2297  case 0x87: { int c = res_N_xix_R<0,A>(addr); NEXT; }
2298  case 0x88: { int c = res_N_xix_R<1,B>(addr); NEXT; }
2299  case 0x89: { int c = res_N_xix_R<1,C>(addr); NEXT; }
2300  case 0x8a: { int c = res_N_xix_R<1,D>(addr); NEXT; }
2301  case 0x8b: { int c = res_N_xix_R<1,E>(addr); NEXT; }
2302  case 0x8c: { int c = res_N_xix_R<1,H>(addr); NEXT; }
2303  case 0x8d: { int c = res_N_xix_R<1,L>(addr); NEXT; }
2304  case 0x8f: { int c = res_N_xix_R<1,A>(addr); NEXT; }
2305  case 0x90: { int c = res_N_xix_R<2,B>(addr); NEXT; }
2306  case 0x91: { int c = res_N_xix_R<2,C>(addr); NEXT; }
2307  case 0x92: { int c = res_N_xix_R<2,D>(addr); NEXT; }
2308  case 0x93: { int c = res_N_xix_R<2,E>(addr); NEXT; }
2309  case 0x94: { int c = res_N_xix_R<2,H>(addr); NEXT; }
2310  case 0x95: { int c = res_N_xix_R<2,L>(addr); NEXT; }
2311  case 0x97: { int c = res_N_xix_R<2,A>(addr); NEXT; }
2312  case 0x98: { int c = res_N_xix_R<3,B>(addr); NEXT; }
2313  case 0x99: { int c = res_N_xix_R<3,C>(addr); NEXT; }
2314  case 0x9a: { int c = res_N_xix_R<3,D>(addr); NEXT; }
2315  case 0x9b: { int c = res_N_xix_R<3,E>(addr); NEXT; }
2316  case 0x9c: { int c = res_N_xix_R<3,H>(addr); NEXT; }
2317  case 0x9d: { int c = res_N_xix_R<3,L>(addr); NEXT; }
2318  case 0x9f: { int c = res_N_xix_R<3,A>(addr); NEXT; }
2319  case 0xa0: { int c = res_N_xix_R<4,B>(addr); NEXT; }
2320  case 0xa1: { int c = res_N_xix_R<4,C>(addr); NEXT; }
2321  case 0xa2: { int c = res_N_xix_R<4,D>(addr); NEXT; }
2322  case 0xa3: { int c = res_N_xix_R<4,E>(addr); NEXT; }
2323  case 0xa4: { int c = res_N_xix_R<4,H>(addr); NEXT; }
2324  case 0xa5: { int c = res_N_xix_R<4,L>(addr); NEXT; }
2325  case 0xa7: { int c = res_N_xix_R<4,A>(addr); NEXT; }
2326  case 0xa8: { int c = res_N_xix_R<5,B>(addr); NEXT; }
2327  case 0xa9: { int c = res_N_xix_R<5,C>(addr); NEXT; }
2328  case 0xaa: { int c = res_N_xix_R<5,D>(addr); NEXT; }
2329  case 0xab: { int c = res_N_xix_R<5,E>(addr); NEXT; }
2330  case 0xac: { int c = res_N_xix_R<5,H>(addr); NEXT; }
2331  case 0xad: { int c = res_N_xix_R<5,L>(addr); NEXT; }
2332  case 0xaf: { int c = res_N_xix_R<5,A>(addr); NEXT; }
2333  case 0xb0: { int c = res_N_xix_R<6,B>(addr); NEXT; }
2334  case 0xb1: { int c = res_N_xix_R<6,C>(addr); NEXT; }
2335  case 0xb2: { int c = res_N_xix_R<6,D>(addr); NEXT; }
2336  case 0xb3: { int c = res_N_xix_R<6,E>(addr); NEXT; }
2337  case 0xb4: { int c = res_N_xix_R<6,H>(addr); NEXT; }
2338  case 0xb5: { int c = res_N_xix_R<6,L>(addr); NEXT; }
2339  case 0xb7: { int c = res_N_xix_R<6,A>(addr); NEXT; }
2340  case 0xb8: { int c = res_N_xix_R<7,B>(addr); NEXT; }
2341  case 0xb9: { int c = res_N_xix_R<7,C>(addr); NEXT; }
2342  case 0xba: { int c = res_N_xix_R<7,D>(addr); NEXT; }
2343  case 0xbb: { int c = res_N_xix_R<7,E>(addr); NEXT; }
2344  case 0xbc: { int c = res_N_xix_R<7,H>(addr); NEXT; }
2345  case 0xbd: { int c = res_N_xix_R<7,L>(addr); NEXT; }
2346  case 0xbf: { int c = res_N_xix_R<7,A>(addr); NEXT; }
2347  case 0x86: { int c = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2348  case 0x8e: { int c = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2349  case 0x96: { int c = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2350  case 0x9e: { int c = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2351  case 0xa6: { int c = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2352  case 0xae: { int c = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2353  case 0xb6: { int c = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2354  case 0xbe: { int c = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2355 
2356  case 0xc0: { int c = set_N_xix_R<0,B>(addr); NEXT; }
2357  case 0xc1: { int c = set_N_xix_R<0,C>(addr); NEXT; }
2358  case 0xc2: { int c = set_N_xix_R<0,D>(addr); NEXT; }
2359  case 0xc3: { int c = set_N_xix_R<0,E>(addr); NEXT; }
2360  case 0xc4: { int c = set_N_xix_R<0,H>(addr); NEXT; }
2361  case 0xc5: { int c = set_N_xix_R<0,L>(addr); NEXT; }
2362  case 0xc7: { int c = set_N_xix_R<0,A>(addr); NEXT; }
2363  case 0xc8: { int c = set_N_xix_R<1,B>(addr); NEXT; }
2364  case 0xc9: { int c = set_N_xix_R<1,C>(addr); NEXT; }
2365  case 0xca: { int c = set_N_xix_R<1,D>(addr); NEXT; }
2366  case 0xcb: { int c = set_N_xix_R<1,E>(addr); NEXT; }
2367  case 0xcc: { int c = set_N_xix_R<1,H>(addr); NEXT; }
2368  case 0xcd: { int c = set_N_xix_R<1,L>(addr); NEXT; }
2369  case 0xcf: { int c = set_N_xix_R<1,A>(addr); NEXT; }
2370  case 0xd0: { int c = set_N_xix_R<2,B>(addr); NEXT; }
2371  case 0xd1: { int c = set_N_xix_R<2,C>(addr); NEXT; }
2372  case 0xd2: { int c = set_N_xix_R<2,D>(addr); NEXT; }
2373  case 0xd3: { int c = set_N_xix_R<2,E>(addr); NEXT; }
2374  case 0xd4: { int c = set_N_xix_R<2,H>(addr); NEXT; }
2375  case 0xd5: { int c = set_N_xix_R<2,L>(addr); NEXT; }
2376  case 0xd7: { int c = set_N_xix_R<2,A>(addr); NEXT; }
2377  case 0xd8: { int c = set_N_xix_R<3,B>(addr); NEXT; }
2378  case 0xd9: { int c = set_N_xix_R<3,C>(addr); NEXT; }
2379  case 0xda: { int c = set_N_xix_R<3,D>(addr); NEXT; }
2380  case 0xdb: { int c = set_N_xix_R<3,E>(addr); NEXT; }
2381  case 0xdc: { int c = set_N_xix_R<3,H>(addr); NEXT; }
2382  case 0xdd: { int c = set_N_xix_R<3,L>(addr); NEXT; }
2383  case 0xdf: { int c = set_N_xix_R<3,A>(addr); NEXT; }
2384  case 0xe0: { int c = set_N_xix_R<4,B>(addr); NEXT; }
2385  case 0xe1: { int c = set_N_xix_R<4,C>(addr); NEXT; }
2386  case 0xe2: { int c = set_N_xix_R<4,D>(addr); NEXT; }
2387  case 0xe3: { int c = set_N_xix_R<4,E>(addr); NEXT; }
2388  case 0xe4: { int c = set_N_xix_R<4,H>(addr); NEXT; }
2389  case 0xe5: { int c = set_N_xix_R<4,L>(addr); NEXT; }
2390  case 0xe7: { int c = set_N_xix_R<4,A>(addr); NEXT; }
2391  case 0xe8: { int c = set_N_xix_R<5,B>(addr); NEXT; }
2392  case 0xe9: { int c = set_N_xix_R<5,C>(addr); NEXT; }
2393  case 0xea: { int c = set_N_xix_R<5,D>(addr); NEXT; }
2394  case 0xeb: { int c = set_N_xix_R<5,E>(addr); NEXT; }
2395  case 0xec: { int c = set_N_xix_R<5,H>(addr); NEXT; }
2396  case 0xed: { int c = set_N_xix_R<5,L>(addr); NEXT; }
2397  case 0xef: { int c = set_N_xix_R<5,A>(addr); NEXT; }
2398  case 0xf0: { int c = set_N_xix_R<6,B>(addr); NEXT; }
2399  case 0xf1: { int c = set_N_xix_R<6,C>(addr); NEXT; }
2400  case 0xf2: { int c = set_N_xix_R<6,D>(addr); NEXT; }
2401  case 0xf3: { int c = set_N_xix_R<6,E>(addr); NEXT; }
2402  case 0xf4: { int c = set_N_xix_R<6,H>(addr); NEXT; }
2403  case 0xf5: { int c = set_N_xix_R<6,L>(addr); NEXT; }
2404  case 0xf7: { int c = set_N_xix_R<6,A>(addr); NEXT; }
2405  case 0xf8: { int c = set_N_xix_R<7,B>(addr); NEXT; }
2406  case 0xf9: { int c = set_N_xix_R<7,C>(addr); NEXT; }
2407  case 0xfa: { int c = set_N_xix_R<7,D>(addr); NEXT; }
2408  case 0xfb: { int c = set_N_xix_R<7,E>(addr); NEXT; }
2409  case 0xfc: { int c = set_N_xix_R<7,H>(addr); NEXT; }
2410  case 0xfd: { int c = set_N_xix_R<7,L>(addr); NEXT; }
2411  case 0xff: { int c = set_N_xix_R<7,A>(addr); NEXT; }
2412  case 0xc6: { int c = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2413  case 0xce: { int c = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2414  case 0xd6: { int c = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2415  case 0xde: { int c = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2416  case 0xe6: { int c = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2417  case 0xee: { int c = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2418  case 0xf6: { int c = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2419  case 0xfe: { int c = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2420  default: UNREACHABLE;
2421  }
2422  }
2423 }
2424 
2425 template<class T> inline void CPUCore<T>::cpuTracePre()
2426 {
2427  start_pc = getPC();
2428 }
2429 template<class T> inline void CPUCore<T>::cpuTracePost()
2430 {
2431  if (unlikely(tracingEnabled)) {
2432  cpuTracePost_slow();
2433  }
2434 }
2435 template<class T> void CPUCore<T>::cpuTracePost_slow()
2436 {
2437  byte opbuf[4];
2438  string dasmOutput;
2439  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2440  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2441  << " : " << dasmOutput
2442  << " AF=" << std::setw(4) << getAF()
2443  << " BC=" << std::setw(4) << getBC()
2444  << " DE=" << std::setw(4) << getDE()
2445  << " HL=" << std::setw(4) << getHL()
2446  << " IX=" << std::setw(4) << getIX()
2447  << " IY=" << std::setw(4) << getIY()
2448  << " SP=" << std::setw(4) << getSP()
2449  << std::endl << std::dec;
2450 }
2451 
2452 template<class T> void CPUCore<T>::executeSlow()
2453 {
2454  if (unlikely(false && nmiEdge)) {
2455  // Note: NMIs are disabled, see also raiseNMI()
2456  nmiEdge = false;
2457  nmi(); // NMI occured
2458  } else if (unlikely(IRQStatus && getIFF1() && !getAfterEI())) {
2459  // normal interrupt
2460  if (unlikely(getAfterLDAI())) {
2461  // HACK!!!
2462  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2463  // bit to the V flag. Though when the Z80 accepts an
2464  // IRQ directly after this instruction, the V flag is 0
2465  // (instead of the expected value 1). This can probably
2466  // be explained if you look at the pipeline of the Z80.
2467  // But for speed reasons we implement it here as a
2468  // fix-up (a hack) in the IRQ routine. This behaviour
2469  // is actually a bug in the Z80.
2470  // Thanks to n_n for reporting this behaviour. I think
2471  // this was discovered by GuyveR800. Also thanks to
2472  // n_n for writing a test program that demonstrates
2473  // this quirk.
2474  // I also wrote a test program that demonstrates this
2475  // behaviour is the same whether 'ld a,i' is preceded
2476  // by a 'ei' instruction or not (so it's not caused by
2477  // the 'delayed IRQ acceptance of ei').
2478  assert(getF() & V_FLAG);
2479  setF(getF() & ~V_FLAG);
2480  }
2481  IRQAccept.signal();
2482  switch (getIM()) {
2483  case 0: irq0();
2484  break;
2485  case 1: irq1();
2486  break;
2487  case 2: irq2();
2488  break;
2489  default:
2490  UNREACHABLE;
2491  }
2492  } else if (unlikely(getHALT())) {
2493  // in halt mode
2494  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2495  setSlowInstructions();
2496  } else {
2497  assert(isSameAfter());
2498  clearNextAfter();
2499  cpuTracePre();
2500  assert(T::limitReached()); // we want only one instruction
2501  executeInstructions();
2502  cpuTracePost();
2503  copyNextAfter();
2504  }
2505 }
2506 
2507 template<class T> void CPUCore<T>::execute(bool fastForward)
2508 {
2509  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2510  // won't trigger. It is possible we already are in break mode, but
2511  // break is ignored in fast-forward mode.
2512  assert(fastForward || !interface->isBreaked());
2513  if (fastForward) {
2514  interface->setFastForward(true);
2515  }
2516  execute2(fastForward);
2517  interface->setFastForward(false);
2518 }
2519 
2520 template<class T> void CPUCore<T>::execute2(bool fastForward)
2521 {
2522  // note: Don't use getTimeFast() here, because 'once in a while' we
2523  // need to CPUClock::sync() to avoid overflow.
2524  // Should be done at least once per second (approx). So only
2525  // once in this method is enough.
2526  scheduler.schedule(T::getTime());
2527  setSlowInstructions();
2528 
2529  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2530  // at least one instruction
2531  interface->setContinue(false);
2532  executeSlow();
2533  scheduler.schedule(T::getTimeFast());
2534  --slowInstructions;
2535  if (interface->isStep()) {
2536  interface->setStep(false);
2537  interface->doBreak();
2538  return;
2539  }
2540  }
2541 
2542  // Note: we call scheduler _after_ executing the instruction and before
2543  // deciding between executeFast() and executeSlow() (because a
2544  // SyncPoint could set an IRQ and then we must choose executeSlow())
2545  if (fastForward ||
2546  (!interface->anyBreakPoints() && !tracingEnabled)) {
2547  // fast path, no breakpoints, no tracing
2548  while (!needExitCPULoop()) {
2549  if (slowInstructions) {
2550  --slowInstructions;
2551  executeSlow();
2552  scheduler.schedule(T::getTimeFast());
2553  } else {
2554  while (slowInstructions == 0) {
2555  T::enableLimit(); // does CPUClock::sync()
2556  if (likely(!T::limitReached())) {
2557  // multiple instructions
2558  assert(isSameAfter());
2559  executeInstructions();
2560  assert(isSameAfter());
2561  }
2562  scheduler.schedule(T::getTimeFast());
2563  if (needExitCPULoop()) return;
2564  }
2565  }
2566  }
2567  } else {
2568  while (!needExitCPULoop()) {
2569  if (interface->checkBreakPoints(getPC())) {
2570  assert(interface->isBreaked());
2571  break;
2572  }
2573  if (slowInstructions == 0) {
2574  cpuTracePre();
2575  assert(T::limitReached()); // only one instruction
2576  assert(isSameAfter());
2577  executeInstructions();
2578  assert(isSameAfter());
2579  cpuTracePost();
2580  } else {
2581  --slowInstructions;
2582  executeSlow();
2583  }
2584  // Don't use getTimeFast() here, we need a call to
2585  // CPUClock::sync() 'once in a while'. (During a
2586  // reverse fast-forward this wasn't always the case).
2587  scheduler.schedule(T::getTime());
2588  }
2589  }
2590 }
2591 
2592 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2593  if (R8 == A) { return getA(); }
2594  else if (R8 == F) { return getF(); }
2595  else if (R8 == B) { return getB(); }
2596  else if (R8 == C) { return getC(); }
2597  else if (R8 == D) { return getD(); }
2598  else if (R8 == E) { return getE(); }
2599  else if (R8 == H) { return getH(); }
2600  else if (R8 == L) { return getL(); }
2601  else if (R8 == IXH) { return getIXh(); }
2602  else if (R8 == IXL) { return getIXl(); }
2603  else if (R8 == IYH) { return getIYh(); }
2604  else if (R8 == IYL) { return getIYl(); }
2605  else if (R8 == REG_I) { return getI(); }
2606  else if (R8 == REG_R) { return getR(); }
2607  else if (R8 == DUMMY) { return 0; }
2608  else { UNREACHABLE; return 0; }
2609 }
2610 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2611  if (R16 == AF) { return getAF(); }
2612  else if (R16 == BC) { return getBC(); }
2613  else if (R16 == DE) { return getDE(); }
2614  else if (R16 == HL) { return getHL(); }
2615  else if (R16 == IX) { return getIX(); }
2616  else if (R16 == IY) { return getIY(); }
2617  else if (R16 == SP) { return getSP(); }
2618  else { UNREACHABLE; return 0; }
2619 }
2620 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2621  if (R8 == A) { setA(x); }
2622  else if (R8 == F) { setF(x); }
2623  else if (R8 == B) { setB(x); }
2624  else if (R8 == C) { setC(x); }
2625  else if (R8 == D) { setD(x); }
2626  else if (R8 == E) { setE(x); }
2627  else if (R8 == H) { setH(x); }
2628  else if (R8 == L) { setL(x); }
2629  else if (R8 == IXH) { setIXh(x); }
2630  else if (R8 == IXL) { setIXl(x); }
2631  else if (R8 == IYH) { setIYh(x); }
2632  else if (R8 == IYL) { setIYl(x); }
2633  else if (R8 == REG_I) { setI(x); }
2634  else if (R8 == REG_R) { setR(x); }
2635  else if (R8 == DUMMY) { /* nothing */ }
2636  else { UNREACHABLE; }
2637 }
2638 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2639  if (R16 == AF) { setAF(x); }
2640  else if (R16 == BC) { setBC(x); }
2641  else if (R16 == DE) { setDE(x); }
2642  else if (R16 == HL) { setHL(x); }
2643  else if (R16 == IX) { setIX(x); }
2644  else if (R16 == IY) { setIY(x); }
2645  else if (R16 == SP) { setSP(x); }
2646  else { UNREACHABLE; }
2647 }
2648 
2649 // LD r,r
2650 template<class T> template<Reg8 DST, Reg8 SRC, int EE> int CPUCore<T>::ld_R_R() {
2651  set8<DST>(get8<SRC>()); return T::CC_LD_R_R + EE;
2652 }
2653 
2654 // LD SP,ss
2655 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_sp_SS() {
2656  setSP(get16<REG>()); return T::CC_LD_SP_HL + EE;
2657 }
2658 
2659 // LD (ss),a
2660 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_a() {
2661  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2662  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2663  return T::CC_LD_SS_A;
2664 }
2665 
2666 // LD (HL),r
2667 template<class T> template<Reg8 SRC> int CPUCore<T>::ld_xhl_R() {
2668  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2669  return T::CC_LD_HL_R;
2670 }
2671 
2672 // LD (IXY+e),r
2673 template<class T> template<Reg16 IXY, Reg8 SRC> int CPUCore<T>::ld_xix_R() {
2674  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_XIX_R_1);
2675  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2676  T::setMemPtr(addr);
2677  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2678  return T::CC_DD + T::CC_LD_XIX_R;
2679 }
2680 
2681 // LD (HL),n
2682 template<class T> int CPUCore<T>::ld_xhl_byte() {
2683  byte val = RDMEM_OPCODE(T::CC_LD_HL_N_1);
2684  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2685  return T::CC_LD_HL_N;
2686 }
2687 
2688 // LD (IXY+e),n
2689 template<class T> template<Reg16 IXY> int CPUCore<T>::ld_xix_byte() {
2690  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_LD_XIX_N_1);
2691  offset ofst = tmp & 0xFF;
2692  byte val = tmp >> 8;
2693  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2694  T::setMemPtr(addr);
2695  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2696  return T::CC_DD + T::CC_LD_XIX_N;
2697 }
2698 
2699 // LD (nn),A
2700 template<class T> int CPUCore<T>::ld_xbyte_a() {
2701  unsigned x = RD_WORD_PC(T::CC_LD_NN_A_1);
2702  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2703  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2704  return T::CC_LD_NN_A;
2705 }
2706 
2707 // LD (nn),ss
2708 template<class T> template<int EE> inline int CPUCore<T>::WR_NN_Y(unsigned reg) {
2709  unsigned addr = RD_WORD_PC(T::CC_LD_XX_HL_1 + EE);
2710  T::setMemPtr(addr + 1);
2711  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2712  return T::CC_LD_XX_HL + EE;
2713 }
2714 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_xword_SS() {
2715  return WR_NN_Y<EE >(get16<REG>());
2716 }
2717 template<class T> template<Reg16 REG> int CPUCore<T>::ld_xword_SS_ED() {
2718  return WR_NN_Y<T::EE_ED>(get16<REG>());
2719 }
2720 
2721 // LD A,(ss)
2722 template<class T> template<Reg16 REG> int CPUCore<T>::ld_a_SS() {
2723  T::setMemPtr(get16<REG>() + 1);
2724  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2725  return T::CC_LD_A_SS;
2726 }
2727 
2728 // LD A,(nn)
2729 template<class T> int CPUCore<T>::ld_a_xbyte() {
2730  unsigned addr = RD_WORD_PC(T::CC_LD_A_NN_1);
2731  T::setMemPtr(addr + 1);
2732  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2733  return T::CC_LD_A_NN;
2734 }
2735 
2736 // LD r,n
2737 template<class T> template<Reg8 DST, int EE> int CPUCore<T>::ld_R_byte() {
2738  set8<DST>(RDMEM_OPCODE(T::CC_LD_R_N_1 + EE)); return T::CC_LD_R_N + EE;
2739 }
2740 
2741 // LD r,(hl)
2742 template<class T> template<Reg8 DST> int CPUCore<T>::ld_R_xhl() {
2743  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return T::CC_LD_R_HL;
2744 }
2745 
2746 // LD r,(IXY+e)
2747 template<class T> template<Reg8 DST, Reg16 IXY> int CPUCore<T>::ld_R_xix() {
2748  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_R_XIX_1);
2749  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2750  T::setMemPtr(addr);
2751  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2752  return T::CC_DD + T::CC_LD_R_XIX;
2753 }
2754 
2755 // LD ss,(nn)
2756 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2757  unsigned addr = RD_WORD_PC(T::CC_LD_HL_XX_1 + EE);
2758  T::setMemPtr(addr + 1);
2759  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2760  return result;
2761 }
2762 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_xword() {
2763  set16<REG>(RD_P_XX<EE>()); return T::CC_LD_HL_XX + EE;
2764 }
2765 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_xword_ED() {
2766  set16<REG>(RD_P_XX<T::EE_ED>()); return T::CC_LD_HL_XX + T::EE_ED;
2767 }
2768 
2769 // LD ss,nn
2770 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_word() {
2771  set16<REG>(RD_WORD_PC(T::CC_LD_SS_NN_1 + EE)); return T::CC_LD_SS_NN + EE;
2772 }
2773 
2774 
2775 // ADC A,r
2776 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2777  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2778  byte f = ((res & 0x100) ? C_FLAG : 0) |
2779  ((getA() ^ res ^ reg) & H_FLAG) |
2780  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2781  0; // N_FLAG
2782  if (T::isR800()) {
2783  f |= ZSTable[res & 0xFF];
2784  f |= getF() & (X_FLAG | Y_FLAG);
2785  } else {
2786  f |= ZSXYTable[res & 0xFF];
2787  }
2788  setF(f);
2789  setA(res);
2790 }
2791 template<class T> inline int CPUCore<T>::adc_a_a() {
2792  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2793  byte f = ((res & 0x100) ? C_FLAG : 0) |
2794  (res & H_FLAG) |
2795  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2796  0; // N_FLAG
2797  if (T::isR800()) {
2798  f |= ZSTable[res & 0xFF];
2799  f |= getF() & (X_FLAG | Y_FLAG);
2800  } else {
2801  f |= ZSXYTable[res & 0xFF];
2802  }
2803  setF(f);
2804  setA(res);
2805  return T::CC_CP_R;
2806 }
2807 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::adc_a_R() {
2808  ADC(get8<SRC>()); return T::CC_CP_R + EE;
2809 }
2810 template<class T> int CPUCore<T>::adc_a_byte() {
2811  ADC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2812 }
2813 template<class T> int CPUCore<T>::adc_a_xhl() {
2814  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2815 }
2816 template<class T> template<Reg16 IXY> int CPUCore<T>::adc_a_xix() {
2817  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2818  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2819  T::setMemPtr(addr);
2820  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2821  return T::CC_DD + T::CC_CP_XIX;
2822 }
2823 
2824 // ADD A,r
2825 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2826  unsigned res = getA() + reg;
2827  byte f = ((res & 0x100) ? C_FLAG : 0) |
2828  ((getA() ^ res ^ reg) & H_FLAG) |
2829  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2830  0; // N_FLAG
2831  if (T::isR800()) {
2832  f |= ZSTable[res & 0xFF];
2833  f |= getF() & (X_FLAG | Y_FLAG);
2834  } else {
2835  f |= ZSXYTable[res & 0xFF];
2836  }
2837  setF(f);
2838  setA(res);
2839 }
2840 template<class T> inline int CPUCore<T>::add_a_a() {
2841  unsigned res = 2 * getA();
2842  byte f = ((res & 0x100) ? C_FLAG : 0) |
2843  (res & H_FLAG) |
2844  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2845  0; // N_FLAG
2846  if (T::isR800()) {
2847  f |= ZSTable[res & 0xFF];
2848  f |= getF() & (X_FLAG | Y_FLAG);
2849  } else {
2850  f |= ZSXYTable[res & 0xFF];
2851  }
2852  setF(f);
2853  setA(res);
2854  return T::CC_CP_R;
2855 }
2856 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::add_a_R() {
2857  ADD(get8<SRC>()); return T::CC_CP_R + EE;
2858 }
2859 template<class T> int CPUCore<T>::add_a_byte() {
2860  ADD(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2861 }
2862 template<class T> int CPUCore<T>::add_a_xhl() {
2863  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2864 }
2865 template<class T> template<Reg16 IXY> int CPUCore<T>::add_a_xix() {
2866  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2867  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2868  T::setMemPtr(addr);
2869  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2870  return T::CC_DD + T::CC_CP_XIX;
2871 }
2872 
2873 // AND r
2874 template<class T> inline void CPUCore<T>::AND(byte reg) {
2875  setA(getA() & reg);
2876  byte f = 0;
2877  if (T::isR800()) {
2878  f |= ZSPHTable[getA()];
2879  f |= getF() & (X_FLAG | Y_FLAG);
2880  } else {
2881  f |= ZSPXYTable[getA()] | H_FLAG;
2882  }
2883  setF(f);
2884 }
2885 template<class T> int CPUCore<T>::and_a() {
2886  byte f = 0;
2887  if (T::isR800()) {
2888  f |= ZSPHTable[getA()];
2889  f |= getF() & (X_FLAG | Y_FLAG);
2890  } else {
2891  f |= ZSPXYTable[getA()] | H_FLAG;
2892  }
2893  setF(f);
2894  return T::CC_CP_R;
2895 }
2896 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::and_R() {
2897  AND(get8<SRC>()); return T::CC_CP_R + EE;
2898 }
2899 template<class T> int CPUCore<T>::and_byte() {
2900  AND(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2901 }
2902 template<class T> int CPUCore<T>::and_xhl() {
2903  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2904 }
2905 template<class T> template<Reg16 IXY> int CPUCore<T>::and_xix() {
2906  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2907  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2908  T::setMemPtr(addr);
2909  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2910  return T::CC_DD + T::CC_CP_XIX;
2911 }
2912 
2913 // CP r
2914 template<class T> inline void CPUCore<T>::CP(byte reg) {
2915  unsigned q = getA() - reg;
2916  byte f = ZSTable[q & 0xFF] |
2917  ((q & 0x100) ? C_FLAG : 0) |
2918  N_FLAG |
2919  ((getA() ^ q ^ reg) & H_FLAG) |
2920  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2921  if (T::isR800()) {
2922  f |= getF() & (X_FLAG | Y_FLAG);
2923  } else {
2924  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2925  }
2926  setF(f);
2927 }
2928 template<class T> int CPUCore<T>::cp_a() {
2929  byte f = ZS0 | N_FLAG;
2930  if (T::isR800()) {
2931  f |= getF() & (X_FLAG | Y_FLAG);
2932  } else {
2933  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2934  }
2935  setF(f);
2936  return T::CC_CP_R;
2937 }
2938 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::cp_R() {
2939  CP(get8<SRC>()); return T::CC_CP_R + EE;
2940 }
2941 template<class T> int CPUCore<T>::cp_byte() {
2942  CP(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2943 }
2944 template<class T> int CPUCore<T>::cp_xhl() {
2945  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2946 }
2947 template<class T> template<Reg16 IXY> int CPUCore<T>::cp_xix() {
2948  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2949  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2950  T::setMemPtr(addr);
2951  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2952  return T::CC_DD + T::CC_CP_XIX;
2953 }
2954 
2955 // OR r
2956 template<class T> inline void CPUCore<T>::OR(byte reg) {
2957  setA(getA() | reg);
2958  byte f = 0;
2959  if (T::isR800()) {
2960  f |= ZSPTable[getA()];
2961  f |= getF() & (X_FLAG | Y_FLAG);
2962  } else {
2963  f |= ZSPXYTable[getA()];
2964  }
2965  setF(f);
2966 }
2967 template<class T> int CPUCore<T>::or_a() {
2968  byte f = 0;
2969  if (T::isR800()) {
2970  f |= ZSPTable[getA()];
2971  f |= getF() & (X_FLAG | Y_FLAG);
2972  } else {
2973  f |= ZSPXYTable[getA()];
2974  }
2975  setF(f);
2976  return T::CC_CP_R;
2977 }
2978 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::or_R() {
2979  OR(get8<SRC>()); return T::CC_CP_R + EE;
2980 }
2981 template<class T> int CPUCore<T>::or_byte() {
2982  OR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2983 }
2984 template<class T> int CPUCore<T>::or_xhl() {
2985  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2986 }
2987 template<class T> template<Reg16 IXY> int CPUCore<T>::or_xix() {
2988  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2989  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2990  T::setMemPtr(addr);
2991  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2992  return T::CC_DD + T::CC_CP_XIX;
2993 }
2994 
2995 // SBC A,r
2996 template<class T> inline void CPUCore<T>::SBC(byte reg) {
2997  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
2998  byte f = ((res & 0x100) ? C_FLAG : 0) |
2999  N_FLAG |
3000  ((getA() ^ res ^ reg) & H_FLAG) |
3001  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3002  if (T::isR800()) {
3003  f |= ZSTable[res & 0xFF];
3004  f |= getF() & (X_FLAG | Y_FLAG);
3005  } else {
3006  f |= ZSXYTable[res & 0xFF];
3007  }
3008  setF(f);
3009  setA(res);
3010 }
3011 template<class T> int CPUCore<T>::sbc_a_a() {
3012  if (T::isR800()) {
3013  word t = (getF() & C_FLAG)
3014  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3015  : ( 0 * 256 | ZS0 | N_FLAG);
3016  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3017  } else {
3018  setAF((getF() & C_FLAG) ?
3019  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3020  ( 0 * 256 | ZSXY0 | N_FLAG));
3021  }
3022  return T::CC_CP_R;
3023 }
3024 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sbc_a_R() {
3025  SBC(get8<SRC>()); return T::CC_CP_R + EE;
3026 }
3027 template<class T> int CPUCore<T>::sbc_a_byte() {
3028  SBC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3029 }
3030 template<class T> int CPUCore<T>::sbc_a_xhl() {
3031  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3032 }
3033 template<class T> template<Reg16 IXY> int CPUCore<T>::sbc_a_xix() {
3034  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3035  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3036  T::setMemPtr(addr);
3037  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3038  return T::CC_DD + T::CC_CP_XIX;
3039 }
3040 
3041 // SUB r
3042 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3043  unsigned res = getA() - reg;
3044  byte f = ((res & 0x100) ? C_FLAG : 0) |
3045  N_FLAG |
3046  ((getA() ^ res ^ reg) & H_FLAG) |
3047  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3048  if (T::isR800()) {
3049  f |= ZSTable[res & 0xFF];
3050  f |= getF() & (X_FLAG | Y_FLAG);
3051  } else {
3052  f |= ZSXYTable[res & 0xFF];
3053  }
3054  setF(f);
3055  setA(res);
3056 }
3057 template<class T> int CPUCore<T>::sub_a() {
3058  if (T::isR800()) {
3059  word t = 0 * 256 | ZS0 | N_FLAG;
3060  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3061  } else {
3062  setAF(0 * 256 | ZSXY0 | N_FLAG);
3063  }
3064  return T::CC_CP_R;
3065 }
3066 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sub_R() {
3067  SUB(get8<SRC>()); return T::CC_CP_R + EE;
3068 }
3069 template<class T> int CPUCore<T>::sub_byte() {
3070  SUB(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3071 }
3072 template<class T> int CPUCore<T>::sub_xhl() {
3073  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3074 }
3075 template<class T> template<Reg16 IXY> int CPUCore<T>::sub_xix() {
3076  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3077  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3078  T::setMemPtr(addr);
3079  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3080  return T::CC_DD + T::CC_CP_XIX;
3081 }
3082 
3083 // XOR r
3084 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3085  setA(getA() ^ reg);
3086  byte f = 0;
3087  if (T::isR800()) {
3088  f |= ZSPTable[getA()];
3089  f |= getF() & (X_FLAG | Y_FLAG);
3090  } else {
3091  f |= ZSPXYTable[getA()];
3092  }
3093  setF(f);
3094 }
3095 template<class T> int CPUCore<T>::xor_a() {
3096  if (T::isR800()) {
3097  word t = 0 * 256 + ZSP0;
3098  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3099  } else {
3100  setAF(0 * 256 + ZSPXY0);
3101  }
3102  return T::CC_CP_R;
3103 }
3104 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::xor_R() {
3105  XOR(get8<SRC>()); return T::CC_CP_R + EE;
3106 }
3107 template<class T> int CPUCore<T>::xor_byte() {
3108  XOR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3109 }
3110 template<class T> int CPUCore<T>::xor_xhl() {
3111  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3112 }
3113 template<class T> template<Reg16 IXY> int CPUCore<T>::xor_xix() {
3114  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3115  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3116  T::setMemPtr(addr);
3117  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3118  return T::CC_DD + T::CC_CP_XIX;
3119 }
3120 
3121 
3122 // DEC r
3123 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3124  byte res = reg - 1;
3125  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3126  (((res & 0x0F) + 1) & H_FLAG) |
3127  N_FLAG;
3128  if (T::isR800()) {
3129  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3130  f |= ZSTable[res];
3131  } else {
3132  f |= getF() & C_FLAG;
3133  f |= ZSXYTable[res];
3134  }
3135  setF(f);
3136  return res;
3137 }
3138 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::dec_R() {
3139  set8<REG>(DEC(get8<REG>())); return T::CC_INC_R + EE;
3140 }
3141 template<class T> template<int EE> inline int CPUCore<T>::DEC_X(unsigned x) {
3142  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3143  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3144  return T::CC_INC_XHL + EE;
3145 }
3146 template<class T> int CPUCore<T>::dec_xhl() {
3147  return DEC_X<0>(getHL());
3148 }
3149 template<class T> template<Reg16 IXY> int CPUCore<T>::dec_xix() {
3150  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3151  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3152  T::setMemPtr(addr);
3153  return DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3154 }
3155 
3156 // INC r
3157 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3158  reg++;
3159  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3160  (((reg & 0x0F) - 1) & H_FLAG) |
3161  0; // N_FLAG
3162  if (T::isR800()) {
3163  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3164  f |= ZSTable[reg];
3165  } else {
3166  f |= getF() & C_FLAG;
3167  f |= ZSXYTable[reg];
3168  }
3169  setF(f);
3170  return reg;
3171 }
3172 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::inc_R() {
3173  set8<REG>(INC(get8<REG>())); return T::CC_INC_R + EE;
3174 }
3175 template<class T> template<int EE> inline int CPUCore<T>::INC_X(unsigned x) {
3176  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3177  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3178  return T::CC_INC_XHL + EE;
3179 }
3180 template<class T> int CPUCore<T>::inc_xhl() {
3181  return INC_X<0>(getHL());
3182 }
3183 template<class T> template<Reg16 IXY> int CPUCore<T>::inc_xix() {
3184  offset ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3185  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3186  T::setMemPtr(addr);
3187  return INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3188 }
3189 
3190 
3191 // ADC HL,ss
3192 template<class T> template<Reg16 REG> inline int CPUCore<T>::adc_hl_SS() {
3193  unsigned reg = get16<REG>();
3194  T::setMemPtr(getHL() + 1);
3195  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3196  byte f = (res >> 16) | // C_FLAG
3197  0; // N_FLAG
3198  if (T::isR800()) {
3199  f |= getF() & (X_FLAG | Y_FLAG);
3200  }
3201  if (res & 0xFFFF) {
3202  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3203  f |= 0; // Z_FLAG
3204  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3205  if (T::isR800()) {
3206  f |= (res >> 8) & S_FLAG;
3207  } else {
3208  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3209  }
3210  } else {
3211  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3212  f |= Z_FLAG;
3213  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3214  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3215  }
3216  setF(f);
3217  setHL(res);
3218  return T::CC_ADC_HL_SS;
3219 }
3220 template<class T> int CPUCore<T>::adc_hl_hl() {
3221  T::setMemPtr(getHL() + 1);
3222  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3223  byte f = (res >> 16) | // C_FLAG
3224  0; // N_FLAG
3225  if (T::isR800()) {
3226  f |= getF() & (X_FLAG | Y_FLAG);
3227  }
3228  if (res & 0xFFFF) {
3229  f |= 0; // Z_FLAG
3230  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3231  if (T::isR800()) {
3232  f |= (res >> 8) & (H_FLAG | S_FLAG);
3233  } else {
3234  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3235  }
3236  } else {
3237  f |= Z_FLAG;
3238  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3239  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3240  }
3241  setF(f);
3242  setHL(res);
3243  return T::CC_ADC_HL_SS;
3244 }
3245 
3246 // ADD HL/IX/IY,ss
3247 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> int CPUCore<T>::add_SS_TT() {
3248  unsigned reg1 = get16<REG1>();
3249  unsigned reg2 = get16<REG2>();
3250  T::setMemPtr(reg1 + 1);
3251  unsigned res = reg1 + reg2;
3252  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3253  (res >> 16) | // C_FLAG
3254  0; // N_FLAG
3255  if (T::isR800()) {
3256  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3257  } else {
3258  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3259  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3260  }
3261  setF(f);
3262  set16<REG1>(res & 0xFFFF);
3263  return T::CC_ADD_HL_SS + EE;
3264 }
3265 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::add_SS_SS() {
3266  unsigned reg = get16<REG>();
3267  T::setMemPtr(reg + 1);
3268  unsigned res = 2 * reg;
3269  byte f = (res >> 16) | // C_FLAG
3270  0; // N_FLAG
3271  if (T::isR800()) {
3272  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3273  f |= (res >> 8) & H_FLAG;
3274  } else {
3275  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3276  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3277  }
3278  setF(f);
3279  set16<REG>(res & 0xFFFF);
3280  return T::CC_ADD_HL_SS + EE;
3281 }
3282 
3283 // SBC HL,ss
3284 template<class T> template<Reg16 REG> inline int CPUCore<T>::sbc_hl_SS() {
3285  unsigned reg = get16<REG>();
3286  T::setMemPtr(getHL() + 1);
3287  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3288  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3289  N_FLAG;
3290  if (T::isR800()) {
3291  f |= getF() & (X_FLAG | Y_FLAG);
3292  }
3293  if (res & 0xFFFF) {
3294  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3295  f |= 0; // Z_FLAG
3296  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3297  if (T::isR800()) {
3298  f |= (res >> 8) & S_FLAG;
3299  } else {
3300  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3301  }
3302  } else {
3303  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3304  f |= Z_FLAG;
3305  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3306  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3307  }
3308  setF(f);
3309  setHL(res);
3310  return T::CC_ADC_HL_SS;
3311 }
3312 template<class T> int CPUCore<T>::sbc_hl_hl() {
3313  T::setMemPtr(getHL() + 1);
3314  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3315  if (getF() & C_FLAG) {
3316  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3317  if (!T::isR800()) {
3318  f |= X_FLAG | Y_FLAG;
3319  }
3320  setHL(0xFFFF);
3321  } else {
3322  f |= Z_FLAG | N_FLAG;
3323  setHL(0);
3324  }
3325  setF(f);
3326  return T::CC_ADC_HL_SS;
3327 }
3328 
3329 // DEC ss
3330 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::dec_SS() {
3331  set16<REG>(get16<REG>() - 1); return T::CC_INC_SS + EE;
3332 }
3333 
3334 // INC ss
3335 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::inc_SS() {
3336  set16<REG>(get16<REG>() + 1); return T::CC_INC_SS + EE;
3337 }
3338 
3339 
3340 // BIT n,r
3341 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::bit_N_R() {
3342  byte reg = get8<REG>();
3343  byte f = 0; // N_FLAG
3344  if (T::isR800()) {
3345  // this is very different from Z80 (not only XY flags)
3346  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3347  f |= H_FLAG;
3348  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3349  } else {
3350  f |= ZSPHTable[reg & (1 << N)];
3351  f |= getF() & C_FLAG;
3352  f |= reg & (X_FLAG | Y_FLAG);
3353  }
3354  setF(f);
3355  return T::CC_BIT_R;
3356 }
3357 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xhl() {
3358  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3359  byte f = 0; // N_FLAG
3360  if (T::isR800()) {
3361  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3362  f |= H_FLAG;
3363  f |= m ? 0 : Z_FLAG;
3364  } else {
3365  f |= ZSPHTable[m];
3366  f |= getF() & C_FLAG;
3367  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3368  }
3369  setF(f);
3370  return T::CC_BIT_XHL;
3371 }
3372 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xix(unsigned addr) {
3373  T::setMemPtr(addr);
3374  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3375  byte f = 0; // N_FLAG
3376  if (T::isR800()) {
3377  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3378  f |= H_FLAG;
3379  f |= m ? 0 : Z_FLAG;
3380  } else {
3381  f |= ZSPHTable[m];
3382  f |= getF() & C_FLAG;
3383  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3384  }
3385  setF(f);
3386  return T::CC_DD + T::CC_BIT_XIX;
3387 }
3388 
3389 // RES n,r
3390 static inline byte RES(unsigned b, byte reg) {
3391  return reg & ~(1 << b);
3392 }
3393 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_R() {
3394  set8<REG>(RES(N, get8<REG>())); return T::CC_SET_R;
3395 }
3396 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3397  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3398  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3399  return res;
3400 }
3401 template<class T> template<unsigned N> int CPUCore<T>::res_N_xhl() {
3402  RES_X<0>(N, getHL()); return T::CC_SET_XHL;
3403 }
3404 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_xix_R(unsigned a) {
3405  T::setMemPtr(a);
3406  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3407  return T::CC_DD + T::CC_SET_XIX;
3408 }
3409 
3410 // SET n,r
3411 static inline byte SET(unsigned b, byte reg) {
3412  return reg | (1 << b);
3413 }
3414 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_R() {
3415  set8<REG>(SET(N, get8<REG>())); return T::CC_SET_R;
3416 }
3417 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3418  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3419  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3420  return res;
3421 }
3422 template<class T> template<unsigned N> int CPUCore<T>::set_N_xhl() {
3423  SET_X<0>(N, getHL()); return T::CC_SET_XHL;
3424 }
3425 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_xix_R(unsigned a) {
3426  T::setMemPtr(a);
3427  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3428  return T::CC_DD + T::CC_SET_XIX;
3429 }
3430 
3431 // RL r
3432 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3433  byte c = reg >> 7;
3434  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3435  byte f = c ? C_FLAG : 0;
3436  if (T::isR800()) {
3437  f |= ZSPTable[reg];
3438  f |= getF() & (X_FLAG | Y_FLAG);
3439  } else {
3440  f |= ZSPXYTable[reg];
3441  }
3442  setF(f);
3443  return reg;
3444 }
3445 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3446  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3447  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3448  return res;
3449 }
3450 template<class T> template<Reg8 REG> int CPUCore<T>::rl_R() {
3451  set8<REG>(RL(get8<REG>())); return T::CC_SET_R;
3452 }
3453 template<class T> int CPUCore<T>::rl_xhl() {
3454  RL_X<0>(getHL()); return T::CC_SET_XHL;
3455 }
3456 template<class T> template<Reg8 REG> int CPUCore<T>::rl_xix_R(unsigned a) {
3457  T::setMemPtr(a);
3458  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3459  return T::CC_DD + T::CC_SET_XIX;
3460 }
3461 
3462 // RLC r
3463 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3464  byte c = reg >> 7;
3465  reg = (reg << 1) | c;
3466  byte f = c ? C_FLAG : 0;
3467  if (T::isR800()) {
3468  f |= ZSPTable[reg];
3469  f |= getF() & (X_FLAG | Y_FLAG);
3470  } else {
3471  f |= ZSPXYTable[reg];
3472  }
3473  setF(f);
3474  return reg;
3475 }
3476 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3477  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3478  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3479  return res;
3480 }
3481 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_R() {
3482  set8<REG>(RLC(get8<REG>())); return T::CC_SET_R;
3483 }
3484 template<class T> int CPUCore<T>::rlc_xhl() {
3485  RLC_X<0>(getHL()); return T::CC_SET_XHL;
3486 }
3487 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_xix_R(unsigned a) {
3488  T::setMemPtr(a);
3489  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3490  return T::CC_DD + T::CC_SET_XIX;
3491 }
3492 
3493 // RR r
3494 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3495  byte c = reg & 1;
3496  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3497  byte f = c ? C_FLAG : 0;
3498  if (T::isR800()) {
3499  f |= ZSPTable[reg];
3500  f |= getF() & (X_FLAG | Y_FLAG);
3501  } else {
3502  f |= ZSPXYTable[reg];
3503  }
3504  setF(f);
3505  return reg;
3506 }
3507 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3508  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3509  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3510  return res;
3511 }
3512 template<class T> template<Reg8 REG> int CPUCore<T>::rr_R() {
3513  set8<REG>(RR(get8<REG>())); return T::CC_SET_R;
3514 }
3515 template<class T> int CPUCore<T>::rr_xhl() {
3516  RR_X<0>(getHL()); return T::CC_SET_XHL;
3517 }
3518 template<class T> template<Reg8 REG> int CPUCore<T>::rr_xix_R(unsigned a) {
3519  T::setMemPtr(a);
3520  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3521  return T::CC_DD + T::CC_SET_XIX;
3522 }
3523 
3524 // RRC r
3525 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3526  byte c = reg & 1;
3527  reg = (reg >> 1) | (c << 7);
3528  byte f = c ? C_FLAG : 0;
3529  if (T::isR800()) {
3530  f |= ZSPTable[reg];
3531  f |= getF() & (X_FLAG | Y_FLAG);
3532  } else {
3533  f |= ZSPXYTable[reg];
3534  }
3535  setF(f);
3536  return reg;
3537 }
3538 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3539  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3540  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3541  return res;
3542 }
3543 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_R() {
3544  set8<REG>(RRC(get8<REG>())); return T::CC_SET_R;
3545 }
3546 template<class T> int CPUCore<T>::rrc_xhl() {
3547  RRC_X<0>(getHL()); return T::CC_SET_XHL;
3548 }
3549 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_xix_R(unsigned a) {
3550  T::setMemPtr(a);
3551  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3552  return T::CC_DD + T::CC_SET_XIX;
3553 }
3554 
3555 // SLA r
3556 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3557  byte c = reg >> 7;
3558  reg <<= 1;
3559  byte f = c ? C_FLAG : 0;
3560  if (T::isR800()) {
3561  f |= ZSPTable[reg];
3562  f |= getF() & (X_FLAG | Y_FLAG);
3563  } else {
3564  f |= ZSPXYTable[reg];
3565  }
3566  setF(f);
3567  return reg;
3568 }
3569 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3570  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3571  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3572  return res;
3573 }
3574 template<class T> template<Reg8 REG> int CPUCore<T>::sla_R() {
3575  set8<REG>(SLA(get8<REG>())); return T::CC_SET_R;
3576 }
3577 template<class T> int CPUCore<T>::sla_xhl() {
3578  SLA_X<0>(getHL()); return T::CC_SET_XHL;
3579 }
3580 template<class T> template<Reg8 REG> int CPUCore<T>::sla_xix_R(unsigned a) {
3581  T::setMemPtr(a);
3582  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3583  return T::CC_DD + T::CC_SET_XIX;
3584 }
3585 
3586 // SLL r
3587 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3588  assert(!T::isR800()); // this instruction is Z80-only
3589  byte c = reg >> 7;
3590  reg = (reg << 1) | 1;
3591  byte f = c ? C_FLAG : 0;
3592  f |= ZSPXYTable[reg];
3593  setF(f);
3594  return reg;
3595 }
3596 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3597  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3598  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3599  return res;
3600 }
3601 template<class T> template<Reg8 REG> int CPUCore<T>::sll_R() {
3602  set8<REG>(SLL(get8<REG>())); return T::CC_SET_R;
3603 }
3604 template<class T> int CPUCore<T>::sll_xhl() {
3605  SLL_X<0>(getHL()); return T::CC_SET_XHL;
3606 }
3607 template<class T> template<Reg8 REG> int CPUCore<T>::sll_xix_R(unsigned a) {
3608  T::setMemPtr(a);
3609  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3610  return T::CC_DD + T::CC_SET_XIX;
3611 }
3612 template<class T> int CPUCore<T>::sll2() {
3613  assert(T::isR800()); // this instruction is R800-only
3614  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3615  (getA() >> 7) | // C_FLAG
3616  0; // all other flags zero
3617  setF(f);
3618  return T::CC_DD + T::CC_SET_XIX; // TODO
3619 }
3620 
3621 // SRA r
3622 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3623  byte c = reg & 1;
3624  reg = (reg >> 1) | (reg & 0x80);
3625  byte f = c ? C_FLAG : 0;
3626  if (T::isR800()) {
3627  f |= ZSPTable[reg];
3628  f |= getF() & (X_FLAG | Y_FLAG);
3629  } else {
3630  f |= ZSPXYTable[reg];
3631  }
3632  setF(f);
3633  return reg;
3634 }
3635 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3636  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3637  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3638  return res;
3639 }
3640 template<class T> template<Reg8 REG> int CPUCore<T>::sra_R() {
3641  set8<REG>(SRA(get8<REG>())); return T::CC_SET_R;
3642 }
3643 template<class T> int CPUCore<T>::sra_xhl() {
3644  SRA_X<0>(getHL()); return T::CC_SET_XHL;
3645 }
3646 template<class T> template<Reg8 REG> int CPUCore<T>::sra_xix_R(unsigned a) {
3647  T::setMemPtr(a);
3648  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3649  return T::CC_DD + T::CC_SET_XIX;
3650 }
3651 
3652 // SRL R
3653 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3654  byte c = reg & 1;
3655  reg >>= 1;
3656  byte f = c ? C_FLAG : 0;
3657  if (T::isR800()) {
3658  f |= ZSPTable[reg];
3659  f |= getF() & (X_FLAG | Y_FLAG);
3660  } else {
3661  f |= ZSPXYTable[reg];
3662  }
3663  setF(f);
3664  return reg;
3665 }
3666 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3667  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3668  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3669  return res;
3670 }
3671 template<class T> template<Reg8 REG> int CPUCore<T>::srl_R() {
3672  set8<REG>(SRL(get8<REG>())); return T::CC_SET_R;
3673 }
3674 template<class T> int CPUCore<T>::srl_xhl() {
3675  SRL_X<0>(getHL()); return T::CC_SET_XHL;
3676 }
3677 template<class T> template<Reg8 REG> int CPUCore<T>::srl_xix_R(unsigned a) {
3678  T::setMemPtr(a);
3679  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3680  return T::CC_DD + T::CC_SET_XIX;
3681 }
3682 
3683 // RLA RLCA RRA RRCA
3684 template<class T> int CPUCore<T>::rla() {
3685  byte c = getF() & C_FLAG;
3686  byte f = (getA() & 0x80) ? C_FLAG : 0;
3687  if (T::isR800()) {
3688  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3689  } else {
3690  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3691  }
3692  setA((getA() << 1) | (c ? 1 : 0));
3693  if (!T::isR800()) {
3694  f |= getA() & (X_FLAG | Y_FLAG);
3695  }
3696  setF(f);
3697  return T::CC_RLA;
3698 }
3699 template<class T> int CPUCore<T>::rlca() {
3700  setA((getA() << 1) | (getA() >> 7));
3701  byte f = 0;
3702  if (T::isR800()) {
3703  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3704  f |= getA() & C_FLAG;
3705  } else {
3706  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3707  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3708  }
3709  setF(f);
3710  return T::CC_RLA;
3711 }
3712 template<class T> int CPUCore<T>::rra() {
3713  byte c = (getF() & C_FLAG) << 7;
3714  byte f = (getA() & 0x01) ? C_FLAG : 0;
3715  if (T::isR800()) {
3716  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3717  } else {
3718  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3719  }
3720  setA((getA() >> 1) | c);
3721  if (!T::isR800()) {
3722  f |= getA() & (X_FLAG | Y_FLAG);
3723  }
3724  setF(f);
3725  return T::CC_RLA;
3726 }
3727 template<class T> int CPUCore<T>::rrca() {
3728  byte f = getA() & C_FLAG;
3729  if (T::isR800()) {
3730  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3731  } else {
3732  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3733  }
3734  setA((getA() >> 1) | (getA() << 7));
3735  if (!T::isR800()) {
3736  f |= getA() & (X_FLAG | Y_FLAG);
3737  }
3738  setF(f);
3739  return T::CC_RLA;
3740 }
3741 
3742 
3743 // RLD
3744 template<class T> int CPUCore<T>::rld() {
3745  byte val = RDMEM(getHL(), T::CC_RLD_1);
3746  T::setMemPtr(getHL() + 1);
3747  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3748  setA((getA() & 0xF0) | (val >> 4));
3749  byte f = 0;
3750  if (T::isR800()) {
3751  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3752  f |= ZSPTable[getA()];
3753  } else {
3754  f |= getF() & C_FLAG;
3755  f |= ZSPXYTable[getA()];
3756  }
3757  setF(f);
3758  return T::CC_RLD;
3759 }
3760 
3761 // RRD
3762 template<class T> int CPUCore<T>::rrd() {
3763  byte val = RDMEM(getHL(), T::CC_RLD_1);
3764  T::setMemPtr(getHL() + 1);
3765  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3766  setA((getA() & 0xF0) | (val & 0x0F));
3767  byte f = 0;
3768  if (T::isR800()) {
3769  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3770  f |= ZSPTable[getA()];
3771  } else {
3772  f |= getF() & C_FLAG;
3773  f |= ZSPXYTable[getA()];
3774  }
3775  setF(f);
3776  return T::CC_RLD;
3777 }
3778 
3779 
3780 // PUSH ss
3781 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3782  setSP(getSP() - 2);
3783  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3784 }
3785 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::push_SS() {
3786  PUSH<EE>(get16<REG>()); return T::CC_PUSH + EE;
3787 }
3788 
3789 // POP ss
3790 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3791  unsigned addr = getSP();
3792  setSP(addr + 2);
3793  return RD_WORD(addr, T::CC_POP_1 + EE);
3794 }
3795 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::pop_SS() {
3796  set16<REG>(POP<EE>()); return T::CC_POP + EE;
3797 }
3798 
3799 
3800 // CALL nn / CALL cc,nn
3801 template<class T> template<typename COND> int CPUCore<T>::call(COND cond) {
3802  unsigned addr = RD_WORD_PC(T::CC_CALL_1);
3803  T::setMemPtr(addr);
3804  if (cond(getF())) {
3805  PUSH<T::EE_CALL>(getPC());
3806  setPC(addr);
3807  return T::CC_CALL_A;
3808  } else {
3809  return T::CC_CALL_B;
3810  }
3811 }
3812 
3813 
3814 // RST n
3815 template<class T> template<unsigned ADDR> int CPUCore<T>::rst() {
3816  PUSH<0>(getPC());
3817  T::setMemPtr(ADDR);
3818  setPC(ADDR);
3819  return T::CC_RST;
3820 }
3821 
3822 
3823 // RET
3824 template<class T> template<int EE, typename COND> inline int CPUCore<T>::RET(COND cond) {
3825  if (cond(getF())) {
3826  unsigned addr = POP<EE>();
3827  T::setMemPtr(addr);
3828  setPC(addr);
3829  return T::CC_RET_A + EE;
3830  } else {
3831  return T::CC_RET_B + EE;
3832  }
3833 }
3834 template<class T> template<typename COND> int CPUCore<T>::ret(COND cond) {
3835  return RET<T::EE_RET_C>(cond);
3836 }
3837 template<class T> int CPUCore<T>::ret() {
3838  return RET<0>(CondTrue());
3839 }
3840 template<class T> int CPUCore<T>::retn() { // also reti
3841  setIFF1(getIFF2());
3842  setSlowInstructions();
3843  return RET<T::EE_RETN>(CondTrue());
3844 }
3845 
3846 
3847 // JP ss
3848 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::jp_SS() {
3849  setPC(get16<REG>()); T::R800ForcePageBreak(); return T::CC_JP_HL + EE;
3850 }
3851 
3852 // JP nn / JP cc,nn
3853 template<class T> template<typename COND> int CPUCore<T>::jp(COND cond) {
3854  unsigned addr = RD_WORD_PC(T::CC_JP_1);
3855  T::setMemPtr(addr);
3856  if (cond(getF())) {
3857  setPC(addr);
3858  T::R800ForcePageBreak();
3859  return T::CC_JP_A;
3860  } else {
3861  return T::CC_JP_B;
3862  }
3863 }
3864 
3865 // JR e
3866 template<class T> template<typename COND> int CPUCore<T>::jr(COND cond) {
3867  offset ofst = RDMEM_OPCODE(T::CC_JR_1);
3868  if (cond(getF())) {
3869  if ((getPC() & 0xFF) == 0) {
3870  // On R800, when this instruction is located in the
3871  // last two byte of a page (a page is a 256-byte
3872  // (aligned) memory block) and even if we jump back,
3873  // thus fetching the next opcode byte does not cause a
3874  // page-break, there still is one cycle overhead. It's
3875  // as-if there is a page-break.
3876  //
3877  // This could be explained by some (very limited)
3878  // pipeline behaviour in R800: it seems that the
3879  // decision to cause a page-break on the next
3880  // instruction is already made before the jump
3881  // destination address for the current instruction is
3882  // calculated (though a destination address in another
3883  // page is also a reason for a page-break).
3884  //
3885  // It's likely all instructions behave like this, but I
3886  // think we can get away with only explicitly emulating
3887  // this behaviour in the djnz and the jr (conditional
3888  // or not) instructions: all other instructions that
3889  // cause the PC to change in a non-incremental way do
3890  // already force a pagebreak for another reason, so
3891  // this effect is masked. Examples of such instructions
3892  // are: JP, RET, CALL, RST, all repeated block
3893  // instructions, accepting an IRQ, (are there more
3894  // instructions are events that change PC?)
3895  //
3896  // See doc/r800-djnz.txt for more details.
3897  T::R800ForcePageBreak();
3898  }
3899  setPC((getPC() + ofst) & 0xFFFF);
3900  T::setMemPtr(getPC());
3901  return T::CC_JR_A;
3902  } else {
3903  return T::CC_JR_B;
3904  }
3905 }
3906 
3907 // DJNZ e
3908 template<class T> int CPUCore<T>::djnz() {
3909  byte b = getB() - 1;
3910  setB(b);
3911  offset ofst = RDMEM_OPCODE(T::CC_JR_1 + T::EE_DJNZ);
3912  if (b) {
3913  if ((getPC() & 0xFF) == 0) {
3914  // See comment in jr()
3915  T::R800ForcePageBreak();
3916  }
3917  setPC((getPC() + ofst) & 0xFFFF);
3918  T::setMemPtr(getPC());
3919  return T::CC_JR_A + T::EE_DJNZ;
3920  } else {
3921  return T::CC_JR_B + T::EE_DJNZ;
3922  }
3923 }
3924 
3925 // EX (SP),ss
3926 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ex_xsp_SS() {
3927  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3928  T::setMemPtr(res);
3929  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3930  set16<REG>(res);
3931  return T::CC_EX_SP_HL + EE;
3932 }
3933 
3934 // IN r,(c)
3935 template<class T> template<Reg8 REG> int CPUCore<T>::in_R_c() {
3936  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
3937  T::setMemPtr(getBC() + 1);
3938  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
3939  byte f = 0;
3940  if (T::isR800()) {
3941  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3942  f |= ZSPTable[res];
3943  } else {
3944  f |= getF() & C_FLAG;
3945  f |= ZSPXYTable[res];
3946  }
3947  setF(f);
3948  set8<REG>(res);
3949  return T::CC_IN_R_C;
3950 }
3951 
3952 // IN a,(n)
3953 template<class T> int CPUCore<T>::in_a_byte() {
3954  unsigned y = RDMEM_OPCODE(T::CC_IN_A_N_1) + 256 * getA();
3955  T::setMemPtr(y + 1);
3956  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
3957  setA(READ_PORT(y, T::CC_IN_A_N_2));
3958  return T::CC_IN_A_N;
3959 }
3960 
3961 // OUT (c),r
3962 template<class T> template<Reg8 REG> int CPUCore<T>::out_c_R() {
3963  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3964  T::setMemPtr(getBC() + 1);
3965  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
3966  return T::CC_OUT_C_R;
3967 }
3968 template<class T> int CPUCore<T>::out_c_0() {
3969  // TODO not on R800
3970  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3971  T::setMemPtr(getBC() + 1);
3972  byte out_c_x = isTurboR ? 255 : 0;
3973  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
3974  return T::CC_OUT_C_R;
3975 }
3976 
3977 // OUT (n),a
3978 template<class T> int CPUCore<T>::out_byte_a() {
3979  byte port = RDMEM_OPCODE(T::CC_OUT_N_A_1);
3980  unsigned y = (getA() << 8) | port;
3981  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
3982  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
3983  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
3984  return T::CC_OUT_N_A;
3985 }
3986 
3987 
3988 // block CP
3989 template<class T> inline int CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
3990  T::setMemPtr(T::getMemPtr() + increase);
3991  byte val = RDMEM(getHL(), T::CC_CPI_1);
3992  byte res = getA() - val;
3993  setHL(getHL() + increase);
3994  setBC(getBC() - 1);
3995  byte f = ((getA() ^ val ^ res) & H_FLAG) |
3996  ZSTable[res] |
3997  N_FLAG |
3998  (getBC() ? V_FLAG : 0);
3999  if (T::isR800()) {
4000  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4001  } else {
4002  f |= getF() & C_FLAG;
4003  unsigned k = res - ((f & H_FLAG) >> 4);
4004  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4005  f |= k & X_FLAG; // bit 3 -> flag 3
4006  }
4007  setF(f);
4008  if (repeat && getBC() && res) {
4009  setPC(getPC() - 2);
4010  T::setMemPtr(getPC() + 1);
4011  return T::CC_CPIR;
4012  } else {
4013  return T::CC_CPI;
4014  }
4015 }
4016 template<class T> int CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4017 template<class T> int CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4018 template<class T> int CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4019 template<class T> int CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4020 
4021 
4022 // block LD
4023 template<class T> inline int CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4024  byte val = RDMEM(getHL(), T::CC_LDI_1);
4025  WRMEM(getDE(), val, T::CC_LDI_2);
4026  setHL(getHL() + increase);
4027  setDE(getDE() + increase);
4028  setBC(getBC() - 1);
4029  byte f = getBC() ? V_FLAG : 0;
4030  if (T::isR800()) {
4031  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4032  } else {
4033  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4034  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4035  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4036  }
4037  setF(f);
4038  if (repeat && getBC()) {
4039  setPC(getPC() - 2);
4040  T::setMemPtr(getPC() + 1);
4041  return T::CC_LDIR;
4042  } else {
4043  return T::CC_LDI;
4044  }
4045 }
4046 template<class T> int CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4047 template<class T> int CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4048 template<class T> int CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4049 template<class T> int CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4050 
4051 
4052 // block IN
4053 template<class T> inline int CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4054  // TODO R800 flags
4055  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4056  T::setMemPtr(getBC() + increase);
4057  setBC(getBC() - 0x100); // decr before use
4058  byte val = READ_PORT(getBC(), T::CC_INI_1);
4059  WRMEM(getHL(), val, T::CC_INI_2);
4060  setHL(getHL() + increase);
4061  unsigned k = val + ((getC() + increase) & 0xFF);
4062  byte b = getB();
4063  setF(((val & S_FLAG) >> 6) | // N_FLAG
4064  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4065  ZSXYTable[b] |
4066  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4067  if (repeat && b) {
4068  setPC(getPC() - 2);
4069  return T::CC_INIR;
4070  } else {
4071  return T::CC_INI;
4072  }
4073 }
4074 template<class T> int CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4075 template<class T> int CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4076 template<class T> int CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4077 template<class T> int CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4078 
4079 
4080 // block OUT
4081 template<class T> inline int CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4082  // TODO R800 flags
4083  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4084  setHL(getHL() + increase);
4085  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4086  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4087  setBC(getBC() - 0x100); // decr after use
4088  T::setMemPtr(getBC() + increase);
4089  unsigned k = val + getL();
4090  byte b = getB();
4091  setF(((val & S_FLAG) >> 6) | // N_FLAG
4092  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4093  ZSXYTable[b] |
4094  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4095  if (repeat && b) {
4096  setPC(getPC() - 2);
4097  return T::CC_OTIR;
4098  } else {
4099  return T::CC_OUTI;
4100  }
4101 }
4102 template<class T> int CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4103 template<class T> int CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4104 template<class T> int CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4105 template<class T> int CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4106 
4107 
4108 // various
4109 template<class T> int CPUCore<T>::nop() { return T::CC_NOP; }
4110 template<class T> int CPUCore<T>::ccf() {
4111  byte f = 0;
4112  if (T::isR800()) {
4113  // H flag is different from Z80 (and as always XY flags as well)
4114  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4115  } else {
4116  f |= (getF() & C_FLAG) << 4; // H_FLAG
4117  // only set X(Y) flag (don't reset if already set)
4118  if (isTurboR) {
4119  // Y flag is not changed on a turboR-Z80
4120  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4121  f |= (getF() | getA()) & X_FLAG;
4122  } else {
4123  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4124  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4125  }
4126  }
4127  f ^= C_FLAG;
4128  setF(f);
4129  return T::CC_CCF;
4130 }
4131 template<class T> int CPUCore<T>::cpl() {
4132  setA(getA() ^ 0xFF);
4133  byte f = H_FLAG | N_FLAG;
4134  if (T::isR800()) {
4135  f |= getF();
4136  } else {
4137  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4138  f |= getA() & (X_FLAG | Y_FLAG);
4139  }
4140  setF(f);
4141  return T::CC_CPL;
4142 }
4143 template<class T> int CPUCore<T>::daa() {
4144  byte a = getA();
4145  byte f = getF();
4146  byte adjust = 0;
4147  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4148  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4149  if (f & N_FLAG) a -= adjust; else a += adjust;
4150  if (T::isR800()) {
4151  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4152  f |= ZSPTable[a];
4153  } else {
4154  f &= C_FLAG | N_FLAG;
4155  f |= ZSPXYTable[a];
4156  }
4157  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4158  setA(a);
4159  setF(f);
4160  return T::CC_DAA;
4161 }
4162 template<class T> int CPUCore<T>::neg() {
4163  // alternative: LUT word negTable[256]
4164  unsigned a = getA();
4165  unsigned res = -signed(a);
4166  byte f = ((res & 0x100) ? C_FLAG : 0) |
4167  N_FLAG |
4168  ((res ^ a) & H_FLAG) |
4169  ((a & res & 0x80) >> 5); // V_FLAG
4170  if (T::isR800()) {
4171  f |= ZSTable[res & 0xFF];
4172  f |= getF() & (X_FLAG | Y_FLAG);
4173  } else {
4174  f |= ZSXYTable[res & 0xFF];
4175  }
4176  setF(f);
4177  setA(res);
4178  return T::CC_NEG;
4179 }
4180 template<class T> int CPUCore<T>::scf() {
4181  byte f = C_FLAG;
4182  if (T::isR800()) {
4183  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4184  } else {
4185  // only set X(Y) flag (don't reset if already set)
4186  if (isTurboR) {
4187  // Y flag is not changed on a turboR-Z80
4188  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4189  f |= (getF() | getA()) & X_FLAG;
4190  } else {
4191  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4192  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4193  }
4194  }
4195  setF(f);
4196  return T::CC_SCF;
4197 }
4198 
4199 template<class T> int CPUCore<T>::ex_af_af() {
4200  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4201  return T::CC_EX;
4202 }
4203 template<class T> int CPUCore<T>::ex_de_hl() {
4204  unsigned t = getDE(); setDE(getHL()); setHL(t);
4205  return T::CC_EX;
4206 }
4207 template<class T> int CPUCore<T>::exx() {
4208  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4209  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4210  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4211  return T::CC_EX;
4212 }
4213 
4214 template<class T> int CPUCore<T>::di() {
4215  setIFF1(false);
4216  setIFF2(false);
4217  return T::CC_DI;
4218 }
4219 template<class T> int CPUCore<T>::ei() {
4220  setIFF1(true);
4221  setIFF2(true);
4222  setAfterEI(); // no ints directly after this instr
4223  setSlowInstructions();
4224  return T::CC_EI;
4225 }
4226 template<class T> int CPUCore<T>::halt() {
4227  setHALT(true);
4228  setSlowInstructions();
4229 
4230  if (!(getIFF1() || getIFF2())) {
4231  diHaltCallback.execute();
4232  }
4233  return T::CC_HALT;
4234 }
4235 template<class T> template<unsigned N> int CPUCore<T>::im_N() {
4236  setIM(N); return T::CC_IM;
4237 }
4238 
4239 // LD A,I/R
4240 template<class T> template<Reg8 REG> int CPUCore<T>::ld_a_IR() {
4241  setA(get8<REG>());
4242  byte f = getIFF2() ? V_FLAG : 0;
4243  if (T::isR800()) {
4244  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4245  f |= ZSTable[getA()];
4246  } else {
4247  f |= getF() & C_FLAG;
4248  f |= ZSXYTable[getA()];
4249  // see comment in the IRQ acceptance part of executeSlow().
4250  setAfterLDAI(); // only Z80 (not R800) has this quirk
4251  setSlowInstructions();
4252  }
4253  setF(f);
4254  return T::CC_LD_A_I;
4255 }
4256 
4257 // LD I/R,A
4258 template<class T> int CPUCore<T>::ld_r_a() {
4259  // This code sequence:
4260  // XOR A / LD R,A / LD A,R
4261  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4262  // explained by a difference in the relative time between writing the
4263  // new value to the R register and increasing the R register per M1
4264  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4265  // R, that's good enough for now.
4266  byte val = getA();
4267  if (T::isR800()) val -= 1;
4268  setR(val);
4269  return T::CC_LD_A_I;
4270 }
4271 template<class T> int CPUCore<T>::ld_i_a() {
4272  setI(getA());
4273  return T::CC_LD_A_I;
4274 }
4275 
4276 // MULUB A,r
4277 template<class T> template<Reg8 REG> int CPUCore<T>::mulub_a_R() {
4278  assert(T::isR800()); // this instruction is R800-only
4279  // Verified on real R800:
4280  // YHXN flags are unchanged
4281  // SV flags are reset
4282  // Z flag is set when result is zero
4283  // C flag is set when result doesn't fit in 8-bit
4284  setHL(unsigned(getA()) * get8<REG>());
4285  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4286  0 | // S_FLAG V_FLAG
4287  (getHL() ? 0 : Z_FLAG) |
4288  ((getHL() & 0xFF00) ? C_FLAG : 0));
4289  return T::CC_MULUB;
4290 }
4291 
4292 // MULUW HL,ss
4293 template<class T> template<Reg16 REG> int CPUCore<T>::muluw_hl_SS() {
4294  assert(T::isR800()); // this instruction is R800-only
4295  // Verified on real R800:
4296  // YHXN flags are unchanged
4297  // SV flags are reset
4298  // Z flag is set when result is zero
4299  // C flag is set when result doesn't fit in 16-bit
4300  unsigned res = unsigned(getHL()) * get16<REG>();
4301  setDE(res >> 16);
4302  setHL(res & 0xffff);
4303  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4304  0 | // S_FLAG V_FLAG
4305  (res ? 0 : Z_FLAG) |
4306  ((res & 0xFFFF0000) ? C_FLAG : 0));
4307  return T::CC_MULUW;
4308 }
4309 
4310 
4311 // versions:
4312 // 1 -> initial version
4313 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4314 // 3 -> timing of the emulation changed (no changes in serialization)
4315 template<class T> template<typename Archive>
4316 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4317 {
4318  T::serialize(ar, version);
4319  ar.serialize("regs", static_cast<CPURegs&>(*this));
4320  if (ar.versionBelow(version, 2)) {
4321  unsigned memptr = 0; // dummy value (avoid warning)
4322  ar.serialize("memptr", memptr);
4323  T::setMemPtr(memptr);
4324  }
4325 
4326  if (ar.isLoader()) {
4327  invalidateMemCache(0x0000, 0x10000);
4328  }
4329 
4330  // don't serialize
4331  // IRQStatus
4332  // NMIStatus, nmiEdge
4333  // slowInstructions
4334  // exitLoop
4335 
4336  if (T::isR800() && ar.versionBelow(version, 3)) {
4337  motherboard.getMSXCliComm().printWarning(
4338  "Loading an old savestate: the timing of the R800 "
4339  "emulation has changed. This may cause synchronization "
4340  "problems in replay.");
4341  }
4342 }
4343 
4344 // Force template instantiation
4345 template class CPUCore<Z80TYPE>;
4346 template class CPUCore<R800TYPE>;
4347 
4350 
4351 } // namespace openmsx
signed char offset
Definition: CPUCore.cc:249
#define CASE(X)
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:360
bool operator()(byte f) const
Definition: CPUCore.cc:260
bool operator()(byte f) const
Definition: CPUCore.cc:258
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:345
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:486
size_type size() const
Definition: array_ref.hh:61
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:425
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:547
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:27
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:520
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:480
bool operator()(byte f) const
Definition: CPUCore.cc:264
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
bool operator()(byte f) const
Definition: CPUCore.cc:261
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:297
bool operator()(byte f) const
Definition: CPUCore.cc:259
bool operator()(byte) const
Definition: CPUCore.cc:266
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:430
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:504
#define NEXT
#define NEXT_STOP
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
bool operator()(byte f) const
Definition: CPUCore.cc:262
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:32
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:452
void waitCycles(unsigned cycles)
Definition: CPUCore.cc:499
static const int CLOCK_FREQ
Definition: Z80.hh:17
bool operator()(byte f) const
Definition: CPUCore.cc:265
void execute(bool fastForward)
Definition: CPUCore.cc:2507
void addListElement(string_ref element)
Definition: TclObject.cc:120
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:461
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void wait(EmuTime::param time)
Definition: CPUCore.cc:492
#define NEXT_EI
void warp(EmuTime::param time)
Definition: CPUCore.cc:339
#define likely(x)
Definition: likely.hh:14
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4316
size_t size(string_ref utf8)
bool operator()(byte f) const
Definition: CPUCore.cc:263
void serialize(Archive &ar, T &t, unsigned version)
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:467
static bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:19
void invalidateMemCache(unsigned start, unsigned size)
Definition: CPUCore.cc:350
#define UNREACHABLE
Definition: unreachable.hh:35