openMSX
CPUCore.cc
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1 // MEMORY EMULATION
2 // ----------------
3 //
4 // Memory access emulation is a very important part of the CPU emulation.
5 // Because they happen so frequently they really need to be executed as fast as
6 // possible otherwise they will completely bring down the speed of the CPU
7 // emulation.
8 //
9 // A very fast way to emulate memory accesses is by simply reading/writing to a
10 // 64kb array (for a 16-bit address space). Unfortunately this doesn't allow
11 // for memory mapped IO (MMIO). These are memory regions where read/writes
12 // trigger side effects, so where we need to execute device-specific code on
13 // read or writes. An alternative that does work with MMIO is for every access
14 // execute a virtual method call, (this is the approach taken by most current
15 // MSX emulators). Unfortunately this is also a lot slower.
16 //
17 // It is possible to combine the speed of array accesses with the flexibility
18 // of virtual methods. In openMSX it's implemened as follows: the 64kb address
19 // space is divided in 256 regions of 256 bytes (called cacheLines in the code
20 // below). For each such region we store a pointer, if this pointer is nullptr
21 // then we have to use the slow way (=virtual method call). If it is not nullptr,
22 // the pointer points to a block of memory that can be directly accessed. In
23 // some contexts accesses via the pointer are known as backdoor accesses while
24 // the accesses directly to the device are known as frontdoor accesses.
25 //
26 // We keep different pointers for read and write accesses. This allows to also
27 // implement ROMs efficiently: read is handled as regular RAM, but writes end
28 // up in some dummy memory region. This region is called 'unmappedWrite' in the
29 // code. There is also a special region 'unmappedRead', this region is filled
30 // with 0xFF and can be used to model (parts of) a device that don't react to
31 // reads (so reads return 0xFF).
32 //
33 // Because of bankswitching (the MSX slot select mechanism, but also e.g.
34 // MegaROM backswitching) the memory map as seen by the Z80 is not static. This
35 // means that the cacheLine pointers also need to change during runtime. To
36 // solve this we made the bankswitch code also responsible for invalidating the
37 // cacheLines of the switched region. These pointers are filled-in again in a
38 // lazy way: the first read or write to a cache line will first get this
39 // pointer (see getReadCacheLine() and getWriteCacheLine() in the code below),
40 // from then on this pointer is used for all further accesses to this region,
41 // until the cache is invalidated again.
42 //
43 //
44 // INSTRUCTION EMULATION
45 // ---------------------
46 //
47 // UPDATE: the 'threaded interpreter model' is not enabled by default
48 // main reason is the huge memory requirement while compiling
49 // and that it doesn't work on non-gcc compilers
50 //
51 // The current implementation is based on a 'threaded interpreter model'. In
52 // the text below I'll call the older implementation the 'traditional
53 // interpreter model'. From a very high level these two models look like this:
54 //
55 // Traditional model:
56 // while (!needExit()) {
57 // byte opcode = fetch(PC++);
58 // switch (opcode) {
59 // case 0x00: nop(); break;
60 // case 0x01: ld_bc_nn(); break;
61 // ...
62 // }
63 // }
64 //
65 // Threaded model:
66 // byte opcode = fetch(PC++); //
67 // goto *(table[opcode]); // fetch-and-dispatch
68 // // note: the goto * syntax is a gcc extension called computed-gotos
69 //
70 // op00: nop(); if (!needExit()) [fetch-and-dispatch];
71 // op01: ld_bc_nn(); if (!needExit()) [fetch-and-dispatch];
72 // ...
73 //
74 // In the first model there is a central place in the code that fetches (the
75 // first byte of) the instruction and based on this byte jumps to the
76 // appropriate routine. In the second model, this fetch-and-dispatch logic is
77 // duplicated at the end of each instruction.
78 //
79 // Typically the 'dispatch' part in above paragraph is implemented (either by
80 // the compiler or manually using computed goto's) via a jump table. Thus on
81 // assembler level via an indirect jump. For the host CPU it's hard to predict
82 // the destination address of such an indirect jump, certainly if there's only
83 // one such jump for all dispatching (the traditional model). If each
84 // instruction has its own indirect jump instruction (the threaded model), it
85 // becomes a bit easier, because often one particular z80 instructions is
86 // followed by a specific other z80 instruction (or one from a small subset).
87 // For example a z80 'cp' instruction is most likely followed by a 'conditional
88 // jump' z80 instruction. Modern CPUs are quite sensitive to
89 // branch-(mis)predictions, so the above optimization helps quite a lot. I
90 // measured a speedup of more than 10%!
91 //
92 // There is another advantage to the threaded model. Because also the
93 // needExit() test is duplicated for each instruction, it becomes possible to
94 // tweak it for individual instructions. But first let me explain this
95 // exit-test in more detail.
96 //
97 // These are the main reasons why the emulator should stop emulating CPU
98 // instructions:
99 // 1) When other devices than the CPU must be emulated (e.g. video frame
100 // rendering). In openMSX this is handled by the Scheduler class and
101 // actually we don't exit the CPU loop (anymore) for this. Instead we
102 // simply execute the device code as a subroutine. Each time right before
103 // we access an IO port or do a frontdoor memory access, there is a check
104 // whether we should emulate device code (search for schedule() in the code
105 // below).
106 // 2) To keep the inner CPU loop as fast as possible we don't check for IRQ,
107 // NMI or HALT status in this loop. Instead this condition is checked only
108 // once at the beginning outside of the loop (if there wasn't a pending IRQ
109 // on the first instruction there also won't be one on the second
110 // instruction, if all we did was emulating cpu instructions). Now when one
111 // of these conditions changes, we must exit the inner loop and re-evaluate
112 // them. For example after an EI instruction we must check the IRQ status
113 // again.
114 // 3) Various reasons like:
115 // * Z80/R800 switch
116 // * executing a Tcl command (could be a cpu-register debug read)
117 // * exit the emulator
118 // 4) 'once-in-a-while': To avoid threading problems and race conditions,
119 // several threads in openMSX only 'schedule' work that will later be
120 // executed by the main emulation thread. The main thread checks for such
121 // task outside of the cpu emulation loop. So once-in-a-while we need to
122 // exit the loop. The exact timing doesn't matter here because anyway the
123 // relative timing between threads is undefined.
124 // So for 1) we don't need to do anything (we don't actually exit). For 2) and
125 // 3) we need the exit the loop as soon as possible (right after the current
126 // instruction is finished). For 4) it's OK to exit 'eventually' (a few hundred
127 // z80 instructions late is still OK).
128 //
129 // Condition 2) is implemented with the 'slowInstructions' mechanism. Condition
130 // 3) via exitCPULoopSync() (may only get called by the main emulation thread)
131 // and condition 4) is implemented via exitCPULoopAsync() (can be called from
132 // any thread).
133 //
134 // Now back to the exit-test optimization: in the threaded model each
135 // instruction ends with:
136 //
137 // if (needExit()) return
138 // byte opcode = fetch(PC++);
139 // goto *(table[opcode]);
140 //
141 // And if we look in more detail at fetch():
142 //
143 // if (canDoBackdoor(addr)) {
144 // doBackdoorAccess(addr);
145 // } else {
146 // doFrontdoorAccess(addr);
147 // }
148 //
149 // So there are in fact two checks per instruction. This can be reduced to only
150 // one check with the following trick:
151 //
152 // !!!WRONG!!!
153 // In the past we optimized this to only check canDoBackdoor() (and make sure
154 // canDoBackdoor() returned false when needExit() would return true). This
155 // worked rather well, except for one case: when we exit the CPU loop we also
156 // check for pending Syncronization points. It is possible such a SyncPoint
157 // raises the IRQ line. So it is important to check for exit after every
158 // instruction, otherwise we would enter the IRQ routine a couple of
159 // instructions too late.
160 
161 #include "CPUCore.hh"
162 #include "MSXCPUInterface.hh"
163 #include "Scheduler.hh"
164 #include "MSXMotherBoard.hh"
165 #include "CliComm.hh"
166 #include "TclCallback.hh"
167 #include "Dasm.hh"
168 #include "Z80.hh"
169 #include "R800.hh"
170 #include "Thread.hh"
171 #include "endian.hh"
172 #include "likely.hh"
173 #include "inline.hh"
174 #include "unreachable.hh"
175 #include <iomanip>
176 #include <iostream>
177 #include <type_traits>
178 #include <cassert>
179 #include <cstring>
180 
181 
182 //
183 // #define USE_COMPUTED_GOTO
184 //
185 // Computed goto's are not enabled by default:
186 // - Computed goto's are a gcc extension, it's not part of the official c++
187 // standard. So this will only work if you use gcc as your compiler (it
188 // won't work with visual c++ for example)
189 // - This is only beneficial on CPUs with branch prediction for indirect jumps
190 // and a reasonable amout of cache. For example it is very benefical for a
191 // intel core2 cpu (10% faster), but not for a ARM920 (a few percent slower)
192 // - Compiling src/cpu/CPUCore.cc with computed goto's enabled is very demanding
193 // on the compiler. On older gcc versions it requires up to 1.5GB of memory.
194 // But even on more recent gcc versions it still requires around 700MB.
195 //
196 // Probably the easiest way to enable this, is to pass the -DUSE_COMPUTED_GOTO
197 // flag to the compiler. This is for example done in the super-opt flavour.
198 // See build/flavour-super-opt.mk
199 
200 
201 using std::string;
202 
203 namespace openmsx {
204 
205 // This actually belongs in Z80.cc and R800.cc (these files don't exist yet).
206 // As a quick hack I put these two lines here because I found it overkill to
207 // create two files each containing only a single line.
208 // Technically these two lines _are_ required according to the c++ standard.
209 // Though usually it works just find without them, but during experiments I did
210 // get a link error when these lines were missing (it only happened during a
211 // debug build with some specific compiler version and only with some
212 // combination of other code changes, but again when strictly following the
213 // language rules, these lines should be here).
214 // ... But visual studio is not fully standard compliant, see also comment
215 // in SectorAccesibleDisk.cc
216 #ifndef _MSC_VER
217 const int Z80TYPE ::CLOCK_FREQ;
218 const int R800TYPE::CLOCK_FREQ;
219 #endif
220 
221 enum Reg8 : int { A, F, B, C, D, E, H, L, IXH, IXL, IYH, IYL, REG_I, REG_R, DUMMY };
222 enum Reg16 : int { AF, BC, DE, HL, IX, IY, SP };
223 
224 // flag positions
225 static const byte S_FLAG = 0x80;
226 static const byte Z_FLAG = 0x40;
227 static const byte Y_FLAG = 0x20;
228 static const byte H_FLAG = 0x10;
229 static const byte X_FLAG = 0x08;
230 static const byte V_FLAG = 0x04;
231 static const byte P_FLAG = V_FLAG;
232 static const byte N_FLAG = 0x02;
233 static const byte C_FLAG = 0x01;
234 
235 // flag-register tables, initialized at run-time
236 static byte ZSTable[256];
237 static byte ZSXYTable[256];
238 static byte ZSPTable[256];
239 static byte ZSPXYTable[256];
240 static byte ZSPHTable[256];
241 
242 static const byte ZS0 = Z_FLAG;
243 static const byte ZSXY0 = Z_FLAG;
244 static const byte ZSP0 = Z_FLAG | V_FLAG;
245 static const byte ZSPXY0 = Z_FLAG | V_FLAG;
246 static const byte ZS255 = S_FLAG;
247 static const byte ZSXY255 = S_FLAG | X_FLAG | Y_FLAG;
248 
249 // Global variable, because it should be shared between Z80 and R800.
250 // It must not be shared between the CPUs of different MSX machines, but
251 // the (logical) lifetime of this variable cannot overlap between execution
252 // of two MSX machines.
253 static word start_pc;
254 
255 // conditions
256 struct CondC { bool operator()(byte f) const { return (f & C_FLAG) != 0; } };
257 struct CondNC { bool operator()(byte f) const { return !(f & C_FLAG); } };
258 struct CondZ { bool operator()(byte f) const { return (f & Z_FLAG) != 0; } };
259 struct CondNZ { bool operator()(byte f) const { return !(f & Z_FLAG); } };
260 struct CondM { bool operator()(byte f) const { return (f & S_FLAG) != 0; } };
261 struct CondP { bool operator()(byte f) const { return !(f & S_FLAG); } };
262 struct CondPE { bool operator()(byte f) const { return (f & V_FLAG) != 0; } };
263 struct CondPO { bool operator()(byte f) const { return !(f & V_FLAG); } };
264 struct CondTrue { bool operator()(byte) const { return true; } };
265 
266 static void initTables()
267 {
268  static bool alreadyInit = false;
269  if (alreadyInit) return;
270  alreadyInit = true;
271 
272  for (int i = 0; i < 256; ++i) {
273  byte zFlag = (i == 0) ? Z_FLAG : 0;
274  byte sFlag = i & S_FLAG;
275  byte xFlag = i & X_FLAG;
276  byte yFlag = i & Y_FLAG;
277  byte vFlag = V_FLAG;
278  for (int v = 128; v != 0; v >>= 1) {
279  if (i & v) vFlag ^= V_FLAG;
280  }
281  ZSTable [i] = zFlag | sFlag;
282  ZSXYTable [i] = zFlag | sFlag | xFlag | yFlag;
283  ZSPTable [i] = zFlag | sFlag | vFlag;
284  ZSPXYTable[i] = zFlag | sFlag | xFlag | yFlag | vFlag;
285  ZSPHTable [i] = zFlag | sFlag | vFlag | H_FLAG;
286  }
287  assert(ZSTable [ 0] == ZS0);
288  assert(ZSXYTable [ 0] == ZSXY0);
289  assert(ZSPTable [ 0] == ZSP0);
290  assert(ZSPXYTable[ 0] == ZSPXY0);
291  assert(ZSTable [255] == ZS255);
292  assert(ZSXYTable [255] == ZSXY255);
293 }
294 
295 template<class T> CPUCore<T>::CPUCore(
296  MSXMotherBoard& motherboard_, const string& name,
297  const BooleanSetting& traceSetting_,
298  TclCallback& diHaltCallback_, EmuTime::param time)
299  : CPURegs(T::isR800())
300  , T(time, motherboard_.getScheduler())
301  , motherboard(motherboard_)
302  , scheduler(motherboard.getScheduler())
303  , interface(nullptr)
304  , traceSetting(traceSetting_)
305  , diHaltCallback(diHaltCallback_)
306  , IRQStatus(motherboard.getDebugger(), name + ".pendingIRQ",
307  "Non-zero if there are pending IRQs (thus CPU would enter "
308  "interrupt routine in EI mode).",
309  0)
310  , IRQAccept(motherboard.getDebugger(), name + ".acceptIRQ",
311  "This probe is only useful to set a breakpoint on (the value "
312  "return by read is meaningless). The breakpoint gets triggered "
313  "right after the CPU accepted an IRQ.")
314  , freqLocked(
315  motherboard.getCommandController(), name + "_freq_locked",
316  "real (locked) or custom (unlocked) " + name + " frequency",
317  true)
318  , freqValue(
319  motherboard.getCommandController(), name + "_freq",
320  "custom " + name + " frequency (only valid when unlocked)",
321  T::CLOCK_FREQ, 1000000, 1000000000)
322  , freq(T::CLOCK_FREQ)
323  , NMIStatus(0)
324  , nmiEdge(false)
325  , exitLoop(false)
326  , tracingEnabled(traceSetting.getBoolean())
327  , isTurboR(motherboard.isTurboR())
328 {
329  static_assert(!std::is_polymorphic<CPUCore<T>>::value,
330  "keep CPUCore non-virtual to keep PC at offset 0");
331  doSetFreq();
332  doReset(time);
333 
334  initTables();
335 }
336 
337 template<class T> void CPUCore<T>::warp(EmuTime::param time)
338 {
339  assert(T::getTimeFast() <= time);
340  T::setTime(time);
341 }
342 
344 {
345  return T::getTime();
346 }
347 
348 template<class T> void CPUCore<T>::invalidateMemCache(unsigned start, unsigned size)
349 {
350  unsigned first = start / CacheLine::SIZE;
351  unsigned num = (size + CacheLine::SIZE - 1) / CacheLine::SIZE;
352  memset(&readCacheLine [first], 0, num * sizeof(byte*)); // nullptr
353  memset(&writeCacheLine [first], 0, num * sizeof(byte*)); //
354  memset(&readCacheTried [first], 0, num * sizeof(bool)); // FALSE
355  memset(&writeCacheTried[first], 0, num * sizeof(bool)); //
356 }
357 
358 template<class T> void CPUCore<T>::doReset(EmuTime::param time)
359 {
360  // AF and SP are 0xFFFF
361  // PC, R, IFF1, IFF2, HALT and IM are 0x0
362  // all others are random
363  setAF(0xFFFF);
364  setBC(0xFFFF);
365  setDE(0xFFFF);
366  setHL(0xFFFF);
367  setIX(0xFFFF);
368  setIY(0xFFFF);
369  setPC(0x0000);
370  setSP(0xFFFF);
371  setAF2(0xFFFF);
372  setBC2(0xFFFF);
373  setDE2(0xFFFF);
374  setHL2(0xFFFF);
375  clearNextAfter();
376  copyNextAfter();
377  setIFF1(false);
378  setIFF2(false);
379  setHALT(false);
380  setExtHALT(false);
381  setIM(0);
382  setI(0x00);
383  setR(0x00);
384  T::setMemPtr(0xFFFF);
385  invalidateMemCache(0x0000, 0x10000);
386 
387  // We expect this assert to be valid
388  // assert(T::getTimeFast() <= time); // time shouldn't go backwards
389  // But it's disabled for the following reason:
390  // 'motion' (IRC nickname) managed to create a replay file that
391  // contains a reset command that falls in the middle of a Z80
392  // instruction. Replayed commands go via the Scheduler, and are
393  // (typically) executed right after a complete CPU instruction. So
394  // the CPU is (slightly) ahead in time of the about to be executed
395  // reset command.
396  // Normally this situation should never occur: console commands,
397  // hotkeys, commands over clicomm, ... are all handled via the global
398  // event mechanism. Such global events are scheduled between CPU
399  // instructions, so also in a replay they should fall between CPU
400  // instructions.
401  // However if for some reason the timing of the emulation changed
402  // (improved emulation accuracy or a bug so that emulation isn't
403  // deterministic or the replay file was edited, ...), then the above
404  // reasoning no longer holds and the assert can trigger.
405  // We need to be robust against loading older replays (when emulation
406  // timing has changed). So in that respect disabling the assert is
407  // good. Though in the example above (motion's replay) it's not clear
408  // whether the assert is really triggered by mixing an old replay
409  // with a newer openMSX version. In any case so far we haven't been
410  // able to reproduce this assert by recording and replaying using a
411  // single openMSX version.
412  T::setTime(time);
413 
414  assert(NMIStatus == 0); // other devices must reset their NMI source
415  assert(IRQStatus == 0); // other devices must reset their IRQ source
416 }
417 
418 // I believe the following two methods are thread safe even without any
419 // locking. The worst that can happen is that we occasionally needlessly
420 // exit the CPU loop, but that's harmless
421 // TODO thread issues are always tricky, can someone confirm this really
422 // is thread safe
423 template<class T> void CPUCore<T>::exitCPULoopAsync()
424 {
425  // can get called from non-main threads
426  exitLoop = true;
427 }
428 template<class T> void CPUCore<T>::exitCPULoopSync()
429 {
430  assert(Thread::isMainThread());
431  exitLoop = true;
432  T::disableLimit();
433 }
434 template<class T> inline bool CPUCore<T>::needExitCPULoop()
435 {
436  // always executed in main thread
437  if (unlikely(exitLoop)) {
438  exitLoop = false;
439  return true;
440  }
441  return false;
442 }
443 
444 template<class T> void CPUCore<T>::setSlowInstructions()
445 {
446  slowInstructions = 2;
447  T::disableLimit();
448 }
449 
450 template<class T> void CPUCore<T>::raiseIRQ()
451 {
452  assert(IRQStatus >= 0);
453  if (IRQStatus == 0) {
454  setSlowInstructions();
455  }
456  IRQStatus = IRQStatus + 1;
457 }
458 
459 template<class T> void CPUCore<T>::lowerIRQ()
460 {
461  IRQStatus = IRQStatus - 1;
462  assert(IRQStatus >= 0);
463 }
464 
465 template<class T> void CPUCore<T>::raiseNMI()
466 {
467  // NMIs are currently disabled, they are anyway not used in MSX and
468  // not having to check for them allows to emulate slightly faster
469  UNREACHABLE;
470  assert(NMIStatus >= 0);
471  if (NMIStatus == 0) {
472  nmiEdge = true;
473  setSlowInstructions();
474  }
475  NMIStatus++;
476 }
477 
478 template<class T> void CPUCore<T>::lowerNMI()
479 {
480  NMIStatus--;
481  assert(NMIStatus >= 0);
482 }
483 
484 template<class T> bool CPUCore<T>::isM1Cycle(unsigned address) const
485 {
486  // PC was already increased, so decrease again
487  return address == ((getPC() - 1) & 0xFFFF);
488 }
489 
490 template<class T> void CPUCore<T>::wait(EmuTime::param time)
491 {
492  assert(time >= getCurrentTime());
493  scheduler.schedule(time);
494  T::advanceTime(time);
495 }
496 
497 template<class T> void CPUCore<T>::waitCycles(unsigned cycles)
498 {
499  T::add(cycles);
500 }
501 
502 template<class T> void CPUCore<T>::setNextSyncPoint(EmuTime::param time)
503 {
504  T::setLimit(time);
505 }
506 
507 
508 static inline char toHex(byte x)
509 {
510  return (x < 10) ? (x + '0') : (x - 10 + 'A');
511 }
512 static void toHex(byte x, char* buf)
513 {
514  buf[0] = toHex(x / 16);
515  buf[1] = toHex(x & 15);
516 }
517 
518 template<class T> void CPUCore<T>::disasmCommand(
519  Interpreter& interp, array_ref<TclObject> tokens, TclObject& result) const
520 {
521  word address = (tokens.size() < 3) ? getPC() : tokens[2].getInt(interp);
522  byte outBuf[4];
523  std::string dasmOutput;
524  unsigned len = dasm(*interface, address, outBuf, dasmOutput,
525  T::getTimeFast());
526  result.addListElement(dasmOutput);
527  char tmp[3]; tmp[2] = 0;
528  for (unsigned i = 0; i < len; ++i) {
529  toHex(outBuf[i], tmp);
530  result.addListElement(tmp);
531  }
532 }
533 
534 template<class T> void CPUCore<T>::update(const Setting& setting)
535 {
536  if (&setting == &freqLocked) {
537  doSetFreq();
538  } else if (&setting == &freqValue) {
539  doSetFreq();
540  } else if (&setting == &traceSetting) {
541  tracingEnabled = traceSetting.getBoolean();
542  }
543 }
544 
545 template<class T> void CPUCore<T>::setFreq(unsigned freq_)
546 {
547  freq = freq_;
548  doSetFreq();
549 }
550 
551 template<class T> void CPUCore<T>::doSetFreq()
552 {
553  if (freqLocked.getBoolean()) {
554  // locked, use value set via setFreq()
555  T::setFreq(freq);
556  } else {
557  // unlocked, use value set by user
558  T::setFreq(freqValue.getInt());
559  }
560 }
561 
562 
563 template<class T> inline byte CPUCore<T>::READ_PORT(unsigned port, unsigned cc)
564 {
565  EmuTime time = T::getTimeFast(cc);
566  scheduler.schedule(time);
567  byte result = interface->readIO(port, time);
568  // note: no forced page-break after IO
569  return result;
570 }
571 
572 template<class T> inline void CPUCore<T>::WRITE_PORT(unsigned port, byte value, unsigned cc)
573 {
574  EmuTime time = T::getTimeFast(cc);
575  scheduler.schedule(time);
576  interface->writeIO(port, value, time);
577  // note: no forced page-break after IO
578 }
579 
580 template<class T> template<bool PRE_PB, bool POST_PB>
581 NEVER_INLINE byte CPUCore<T>::RDMEMslow(unsigned address, unsigned cc)
582 {
583  // not cached
584  unsigned high = address >> CacheLine::BITS;
585  if (!readCacheTried[high]) {
586  // try to cache now
587  unsigned addrBase = address & CacheLine::HIGH;
588  if (const byte* line = interface->getReadCacheLine(addrBase)) {
589  // cached ok
590  T::template PRE_MEM<PRE_PB, POST_PB>(address);
591  T::template POST_MEM< POST_PB>(address);
592  readCacheLine[high] = line - addrBase;
593  return readCacheLine[high][address];
594  }
595  }
596  // uncacheable
597  readCacheTried[high] = true;
598  T::template PRE_MEM<PRE_PB, POST_PB>(address);
599  EmuTime time = T::getTimeFast(cc);
600  scheduler.schedule(time);
601  byte result = interface->readMem(address, time);
602  T::template POST_MEM<POST_PB>(address);
603  return result;
604 }
605 template<class T> template<bool PRE_PB, bool POST_PB>
606 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl2(unsigned address, unsigned cc)
607 {
608  const byte* line = readCacheLine[address >> CacheLine::BITS];
609  if (likely(line != nullptr)) {
610  // cached, fast path
611  T::template PRE_MEM<PRE_PB, POST_PB>(address);
612  T::template POST_MEM< POST_PB>(address);
613  return line[address];
614  } else {
615  return RDMEMslow<PRE_PB, POST_PB>(address, cc); // not inlined
616  }
617 }
618 template<class T> template<bool PRE_PB, bool POST_PB>
619 ALWAYS_INLINE byte CPUCore<T>::RDMEM_impl(unsigned address, unsigned cc)
620 {
621  static const bool PRE = T::template Normalize<PRE_PB >::value;
622  static const bool POST = T::template Normalize<POST_PB>::value;
623  return RDMEM_impl2<PRE, POST>(address, cc);
624 }
625 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM_OPCODE(unsigned cc)
626 {
627  unsigned address = getPC();
628  setPC(address + 1);
629  return RDMEM_impl<false, false>(address, cc);
630 }
631 template<class T> ALWAYS_INLINE byte CPUCore<T>::RDMEM(unsigned address, unsigned cc)
632 {
633  return RDMEM_impl<true, true>(address, cc);
634 }
635 
636 template<class T> template<bool PRE_PB, bool POST_PB>
637 NEVER_INLINE unsigned CPUCore<T>::RD_WORD_slow(unsigned address, unsigned cc)
638 {
639  unsigned res = RDMEM_impl<PRE_PB, false>(address, cc);
640  res += RDMEM_impl<false, POST_PB>((address + 1) & 0xFFFF, cc + T::CC_RDMEM) << 8;
641  return res;
642 }
643 template<class T> template<bool PRE_PB, bool POST_PB>
644 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl2(unsigned address, unsigned cc)
645 {
646  const byte* line = readCacheLine[address >> CacheLine::BITS];
647  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
648  // fast path: cached and two bytes in same cache line
649  T::template PRE_WORD<PRE_PB, POST_PB>(address);
650  T::template POST_WORD< POST_PB>(address);
651  return Endian::read_UA_L16(&line[address]);
652  } else {
653  // slow path, not inline
654  return RD_WORD_slow<PRE_PB, POST_PB>(address, cc);
655  }
656 }
657 template<class T> template<bool PRE_PB, bool POST_PB>
658 ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_impl(unsigned address, unsigned cc)
659 {
660  static const bool PRE = T::template Normalize<PRE_PB >::value;
661  static const bool POST = T::template Normalize<POST_PB>::value;
662  return RD_WORD_impl2<PRE, POST>(address, cc);
663 }
664 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD_PC(unsigned cc)
665 {
666  unsigned addr = getPC();
667  setPC(addr + 2);
668  return RD_WORD_impl<false, false>(addr, cc);
669 }
670 template<class T> ALWAYS_INLINE unsigned CPUCore<T>::RD_WORD(
671  unsigned address, unsigned cc)
672 {
673  return RD_WORD_impl<true, true>(address, cc);
674 }
675 
676 template<class T> template<bool PRE_PB, bool POST_PB>
677 NEVER_INLINE void CPUCore<T>::WRMEMslow(unsigned address, byte value, unsigned cc)
678 {
679  // not cached
680  unsigned high = address >> CacheLine::BITS;
681  if (!writeCacheTried[high]) {
682  // try to cache now
683  unsigned addrBase = address & CacheLine::HIGH;
684  if (byte* line = interface->getWriteCacheLine(addrBase)) {
685  // cached ok
686  T::template PRE_MEM<PRE_PB, POST_PB>(address);
687  T::template POST_MEM< POST_PB>(address);
688  writeCacheLine[high] = line - addrBase;
689  writeCacheLine[high][address] = value;
690  return;
691  }
692  }
693  // uncacheable
694  writeCacheTried[high] = true;
695  T::template PRE_MEM<PRE_PB, POST_PB>(address);
696  EmuTime time = T::getTimeFast(cc);
697  scheduler.schedule(time);
698  interface->writeMem(address, value, time);
699  T::template POST_MEM<POST_PB>(address);
700 }
701 template<class T> template<bool PRE_PB, bool POST_PB>
703  unsigned address, byte value, unsigned cc)
704 {
705  byte* line = writeCacheLine[address >> CacheLine::BITS];
706  if (likely(line != nullptr)) {
707  // cached, fast path
708  T::template PRE_MEM<PRE_PB, POST_PB>(address);
709  T::template POST_MEM< POST_PB>(address);
710  line[address] = value;
711  } else {
712  WRMEMslow<PRE_PB, POST_PB>(address, value, cc); // not inlined
713  }
714 }
715 template<class T> template<bool PRE_PB, bool POST_PB>
717  unsigned address, byte value, unsigned cc)
718 {
719  static const bool PRE = T::template Normalize<PRE_PB >::value;
720  static const bool POST = T::template Normalize<POST_PB>::value;
721  WRMEM_impl2<PRE, POST>(address, value, cc);
722 }
723 template<class T> ALWAYS_INLINE void CPUCore<T>::WRMEM(
724  unsigned address, byte value, unsigned cc)
725 {
726  WRMEM_impl<true, true>(address, value, cc);
727 }
728 
729 template<class T> NEVER_INLINE void CPUCore<T>::WR_WORD_slow(
730  unsigned address, unsigned value, unsigned cc)
731 {
732  WRMEM_impl<true, false>( address, value & 255, cc);
733  WRMEM_impl<false, true>((address + 1) & 0xFFFF, value >> 8, cc + T::CC_WRMEM);
734 }
735 template<class T> ALWAYS_INLINE void CPUCore<T>::WR_WORD(
736  unsigned address, unsigned value, unsigned cc)
737 {
738  byte* line = writeCacheLine[address >> CacheLine::BITS];
739  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
740  // fast path: cached and two bytes in same cache line
741  T::template PRE_WORD<true, true>(address);
742  T::template POST_WORD< true>(address);
743  Endian::write_UA_L16(&line[address], value);
744  } else {
745  // slow path, not inline
746  WR_WORD_slow(address, value, cc);
747  }
748 }
749 
750 // same as WR_WORD, but writes high byte first
751 template<class T> template<bool PRE_PB, bool POST_PB>
753  unsigned address, unsigned value, unsigned cc)
754 {
755  WRMEM_impl<PRE_PB, false>((address + 1) & 0xFFFF, value >> 8, cc);
756  WRMEM_impl<false, POST_PB>( address, value & 255, cc + T::CC_WRMEM);
757 }
758 template<class T> template<bool PRE_PB, bool POST_PB>
760  unsigned address, unsigned value, unsigned cc)
761 {
762  byte* line = writeCacheLine[address >> CacheLine::BITS];
763  if (likely(((address & CacheLine::LOW) != CacheLine::LOW) && line)) {
764  // fast path: cached and two bytes in same cache line
765  T::template PRE_WORD<PRE_PB, POST_PB>(address);
766  T::template POST_WORD< POST_PB>(address);
767  Endian::write_UA_L16(&line[address], value);
768  } else {
769  // slow path, not inline
770  WR_WORD_rev_slow<PRE_PB, POST_PB>(address, value, cc);
771  }
772 }
773 template<class T> template<bool PRE_PB, bool POST_PB>
775  unsigned address, unsigned value, unsigned cc)
776 {
777  static const bool PRE = T::template Normalize<PRE_PB >::value;
778  static const bool POST = T::template Normalize<POST_PB>::value;
779  WR_WORD_rev2<PRE, POST>(address, value, cc);
780 }
781 
782 
783 // NMI interrupt
784 template<class T> inline void CPUCore<T>::nmi()
785 {
786  incR(1);
787  setHALT(false);
788  setIFF1(false);
789  PUSH<T::EE_NMI_1>(getPC());
790  setPC(0x0066);
791  T::add(T::CC_NMI);
792 }
793 
794 // IM0 interrupt
795 template<class T> inline void CPUCore<T>::irq0()
796 {
797  // TODO current implementation only works for 1-byte instructions
798  // ok for MSX
799  assert(interface->readIRQVector() == 0xFF);
800  incR(1);
801  setHALT(false);
802  setIFF1(false);
803  setIFF2(false);
804  PUSH<T::EE_IRQ0_1>(getPC());
805  setPC(0x0038);
806  T::setMemPtr(getPC());
807  T::add(T::CC_IRQ0);
808 }
809 
810 // IM1 interrupt
811 template<class T> inline void CPUCore<T>::irq1()
812 {
813  incR(1);
814  setHALT(false);
815  setIFF1(false);
816  setIFF2(false);
817  PUSH<T::EE_IRQ1_1>(getPC());
818  setPC(0x0038);
819  T::setMemPtr(getPC());
820  T::add(T::CC_IRQ1);
821 }
822 
823 // IM2 interrupt
824 template<class T> inline void CPUCore<T>::irq2()
825 {
826  incR(1);
827  setHALT(false);
828  setIFF1(false);
829  setIFF2(false);
830  PUSH<T::EE_IRQ2_1>(getPC());
831  unsigned x = interface->readIRQVector() | (getI() << 8);
832  setPC(RD_WORD(x, T::CC_IRQ2_2));
833  T::setMemPtr(getPC());
834  T::add(T::CC_IRQ2);
835 }
836 
837 template<class T>
838 void CPUCore<T>::executeInstructions()
839 {
840  assert(isNextAfterClear());
841 
842 #ifdef USE_COMPUTED_GOTO
843  // Addresses of all main-opcode routines,
844  // Note that 40/49/53/5B/64/6D/7F is replaced by 00 (ld r,r == nop)
845  static void* opcodeTable[256] = {
846  &&op00, &&op01, &&op02, &&op03, &&op04, &&op05, &&op06, &&op07,
847  &&op08, &&op09, &&op0A, &&op0B, &&op0C, &&op0D, &&op0E, &&op0F,
848  &&op10, &&op11, &&op12, &&op13, &&op14, &&op15, &&op16, &&op17,
849  &&op18, &&op19, &&op1A, &&op1B, &&op1C, &&op1D, &&op1E, &&op1F,
850  &&op20, &&op21, &&op22, &&op23, &&op24, &&op25, &&op26, &&op27,
851  &&op28, &&op29, &&op2A, &&op2B, &&op2C, &&op2D, &&op2E, &&op2F,
852  &&op30, &&op31, &&op32, &&op33, &&op34, &&op35, &&op36, &&op37,
853  &&op38, &&op39, &&op3A, &&op3B, &&op3C, &&op3D, &&op3E, &&op3F,
854  &&op00, &&op41, &&op42, &&op43, &&op44, &&op45, &&op46, &&op47,
855  &&op48, &&op00, &&op4A, &&op4B, &&op4C, &&op4D, &&op4E, &&op4F,
856  &&op50, &&op51, &&op00, &&op53, &&op54, &&op55, &&op56, &&op57,
857  &&op58, &&op59, &&op5A, &&op00, &&op5C, &&op5D, &&op5E, &&op5F,
858  &&op60, &&op61, &&op62, &&op63, &&op00, &&op65, &&op66, &&op67,
859  &&op68, &&op69, &&op6A, &&op6B, &&op6C, &&op00, &&op6E, &&op6F,
860  &&op70, &&op71, &&op72, &&op73, &&op74, &&op75, &&op76, &&op77,
861  &&op78, &&op79, &&op7A, &&op7B, &&op7C, &&op7D, &&op7E, &&op00,
862  &&op80, &&op81, &&op82, &&op83, &&op84, &&op85, &&op86, &&op87,
863  &&op88, &&op89, &&op8A, &&op8B, &&op8C, &&op8D, &&op8E, &&op8F,
864  &&op90, &&op91, &&op92, &&op93, &&op94, &&op95, &&op96, &&op97,
865  &&op98, &&op99, &&op9A, &&op9B, &&op9C, &&op9D, &&op9E, &&op9F,
866  &&opA0, &&opA1, &&opA2, &&opA3, &&opA4, &&opA5, &&opA6, &&opA7,
867  &&opA8, &&opA9, &&opAA, &&opAB, &&opAC, &&opAD, &&opAE, &&opAF,
868  &&opB0, &&opB1, &&opB2, &&opB3, &&opB4, &&opB5, &&opB6, &&opB7,
869  &&opB8, &&opB9, &&opBA, &&opBB, &&opBC, &&opBD, &&opBE, &&opBF,
870  &&opC0, &&opC1, &&opC2, &&opC3, &&opC4, &&opC5, &&opC6, &&opC7,
871  &&opC8, &&opC9, &&opCA, &&opCB, &&opCC, &&opCD, &&opCE, &&opCF,
872  &&opD0, &&opD1, &&opD2, &&opD3, &&opD4, &&opD5, &&opD6, &&opD7,
873  &&opD8, &&opD9, &&opDA, &&opDB, &&opDC, &&opDD, &&opDE, &&opDF,
874  &&opE0, &&opE1, &&opE2, &&opE3, &&opE4, &&opE5, &&opE6, &&opE7,
875  &&opE8, &&opE9, &&opEA, &&opEB, &&opEC, &&opED, &&opEE, &&opEF,
876  &&opF0, &&opF1, &&opF2, &&opF3, &&opF4, &&opF5, &&opF6, &&opF7,
877  &&opF8, &&opF9, &&opFA, &&opFB, &&opFC, &&opFD, &&opFE, &&opFF,
878  };
879 
880 // Check T::limitReached(). If it's OK to continue,
881 // fetch and execute next instruction.
882 #define NEXT \
883  T::add(c); \
884  T::R800Refresh(*this); \
885  if (likely(!T::limitReached())) { \
886  incR(1); \
887  unsigned address = getPC(); \
888  const byte* line = readCacheLine[address >> CacheLine::BITS]; \
889  if (likely(line != nullptr)) { \
890  setPC(address + 1); \
891  T::template PRE_MEM<false, false>(address); \
892  T::template POST_MEM< false>(address); \
893  byte op = line[address]; \
894  goto *(opcodeTable[op]); \
895  } else { \
896  goto fetchSlow; \
897  } \
898  } \
899  return;
900 
901 // After some instructions we must always exit the CPU loop (ei, halt, retn)
902 #define NEXT_STOP \
903  T::add(c); \
904  T::R800Refresh(*this); \
905  assert(T::limitReached()); \
906  return;
907 
908 #define NEXT_EI \
909  T::add(c); \
910  /* !! NO T::R800Refresh(*this); !! */ \
911  assert(T::limitReached()); \
912  return;
913 
914 // Define a label (instead of case in a switch statement)
915 #define CASE(X) op##X:
916 
917 #else // USE_COMPUTED_GOTO
918 
919 #define NEXT \
920  T::add(c); \
921  T::R800Refresh(*this); \
922  if (likely(!T::limitReached())) { \
923  goto start; \
924  } \
925  return;
926 
927 #define NEXT_STOP \
928  T::add(c); \
929  T::R800Refresh(*this); \
930  assert(T::limitReached()); \
931  return;
932 
933 #define NEXT_EI \
934  T::add(c); \
935  /* !! NO T::R800Refresh(*this); !! */ \
936  assert(T::limitReached()); \
937  return;
938 
939 #define CASE(X) case 0x##X:
940 
941 #endif // USE_COMPUTED_GOTO
942 
943 #ifndef USE_COMPUTED_GOTO
944 start:
945 #endif
946  unsigned ixy; // for dd_cb/fd_cb
947  byte opcodeMain = RDMEM_OPCODE(T::CC_MAIN);
948  incR(1);
949 #ifdef USE_COMPUTED_GOTO
950  goto *(opcodeTable[opcodeMain]);
951 
952 fetchSlow: {
953  unsigned address = getPC();
954  setPC(address + 1);
955  byte opcodeSlow = RDMEMslow<false, false>(address, T::CC_MAIN);
956  goto *(opcodeTable[opcodeSlow]);
957 }
958 #endif
959 
960 #ifndef USE_COMPUTED_GOTO
961 switchopcode:
962  switch (opcodeMain) {
963 CASE(40) // ld b,b
964 CASE(49) // ld c,c
965 CASE(52) // ld d,d
966 CASE(5B) // ld e,e
967 CASE(64) // ld h,h
968 CASE(6D) // ld l,l
969 CASE(7F) // ld a,a
970 #endif
971 CASE(00) { int c = nop(); NEXT; }
972 CASE(07) { int c = rlca(); NEXT; }
973 CASE(0F) { int c = rrca(); NEXT; }
974 CASE(17) { int c = rla(); NEXT; }
975 CASE(1F) { int c = rra(); NEXT; }
976 CASE(08) { int c = ex_af_af(); NEXT; }
977 CASE(27) { int c = daa(); NEXT; }
978 CASE(2F) { int c = cpl(); NEXT; }
979 CASE(37) { int c = scf(); NEXT; }
980 CASE(3F) { int c = ccf(); NEXT; }
981 CASE(20) { int c = jr(CondNZ()); NEXT; }
982 CASE(28) { int c = jr(CondZ ()); NEXT; }
983 CASE(30) { int c = jr(CondNC()); NEXT; }
984 CASE(38) { int c = jr(CondC ()); NEXT; }
985 CASE(18) { int c = jr(CondTrue()); NEXT; }
986 CASE(10) { int c = djnz(); NEXT; }
987 CASE(32) { int c = ld_xbyte_a(); NEXT; }
988 CASE(3A) { int c = ld_a_xbyte(); NEXT; }
989 CASE(22) { int c = ld_xword_SS<HL,0>(); NEXT; }
990 CASE(2A) { int c = ld_SS_xword<HL,0>(); NEXT; }
991 CASE(02) { int c = ld_SS_a<BC>(); NEXT; }
992 CASE(12) { int c = ld_SS_a<DE>(); NEXT; }
993 CASE(1A) { int c = ld_a_SS<DE>(); NEXT; }
994 CASE(0A) { int c = ld_a_SS<BC>(); NEXT; }
995 CASE(03) { int c = inc_SS<BC,0>(); NEXT; }
996 CASE(13) { int c = inc_SS<DE,0>(); NEXT; }
997 CASE(23) { int c = inc_SS<HL,0>(); NEXT; }
998 CASE(33) { int c = inc_SS<SP,0>(); NEXT; }
999 CASE(0B) { int c = dec_SS<BC,0>(); NEXT; }
1000 CASE(1B) { int c = dec_SS<DE,0>(); NEXT; }
1001 CASE(2B) { int c = dec_SS<HL,0>(); NEXT; }
1002 CASE(3B) { int c = dec_SS<SP,0>(); NEXT; }
1003 CASE(09) { int c = add_SS_TT<HL,BC,0>(); NEXT; }
1004 CASE(19) { int c = add_SS_TT<HL,DE,0>(); NEXT; }
1005 CASE(29) { int c = add_SS_SS<HL ,0>(); NEXT; }
1006 CASE(39) { int c = add_SS_TT<HL,SP,0>(); NEXT; }
1007 CASE(01) { int c = ld_SS_word<BC,0>(); NEXT; }
1008 CASE(11) { int c = ld_SS_word<DE,0>(); NEXT; }
1009 CASE(21) { int c = ld_SS_word<HL,0>(); NEXT; }
1010 CASE(31) { int c = ld_SS_word<SP,0>(); NEXT; }
1011 CASE(04) { int c = inc_R<B,0>(); NEXT; }
1012 CASE(0C) { int c = inc_R<C,0>(); NEXT; }
1013 CASE(14) { int c = inc_R<D,0>(); NEXT; }
1014 CASE(1C) { int c = inc_R<E,0>(); NEXT; }
1015 CASE(24) { int c = inc_R<H,0>(); NEXT; }
1016 CASE(2C) { int c = inc_R<L,0>(); NEXT; }
1017 CASE(3C) { int c = inc_R<A,0>(); NEXT; }
1018 CASE(34) { int c = inc_xhl(); NEXT; }
1019 CASE(05) { int c = dec_R<B,0>(); NEXT; }
1020 CASE(0D) { int c = dec_R<C,0>(); NEXT; }
1021 CASE(15) { int c = dec_R<D,0>(); NEXT; }
1022 CASE(1D) { int c = dec_R<E,0>(); NEXT; }
1023 CASE(25) { int c = dec_R<H,0>(); NEXT; }
1024 CASE(2D) { int c = dec_R<L,0>(); NEXT; }
1025 CASE(3D) { int c = dec_R<A,0>(); NEXT; }
1026 CASE(35) { int c = dec_xhl(); NEXT; }
1027 CASE(06) { int c = ld_R_byte<B,0>(); NEXT; }
1028 CASE(0E) { int c = ld_R_byte<C,0>(); NEXT; }
1029 CASE(16) { int c = ld_R_byte<D,0>(); NEXT; }
1030 CASE(1E) { int c = ld_R_byte<E,0>(); NEXT; }
1031 CASE(26) { int c = ld_R_byte<H,0>(); NEXT; }
1032 CASE(2E) { int c = ld_R_byte<L,0>(); NEXT; }
1033 CASE(3E) { int c = ld_R_byte<A,0>(); NEXT; }
1034 CASE(36) { int c = ld_xhl_byte(); NEXT; }
1035 
1036 CASE(41) { int c = ld_R_R<B,C,0>(); NEXT; }
1037 CASE(42) { int c = ld_R_R<B,D,0>(); NEXT; }
1038 CASE(43) { int c = ld_R_R<B,E,0>(); NEXT; }
1039 CASE(44) { int c = ld_R_R<B,H,0>(); NEXT; }
1040 CASE(45) { int c = ld_R_R<B,L,0>(); NEXT; }
1041 CASE(47) { int c = ld_R_R<B,A,0>(); NEXT; }
1042 CASE(48) { int c = ld_R_R<C,B,0>(); NEXT; }
1043 CASE(4A) { int c = ld_R_R<C,D,0>(); NEXT; }
1044 CASE(4B) { int c = ld_R_R<C,E,0>(); NEXT; }
1045 CASE(4C) { int c = ld_R_R<C,H,0>(); NEXT; }
1046 CASE(4D) { int c = ld_R_R<C,L,0>(); NEXT; }
1047 CASE(4F) { int c = ld_R_R<C,A,0>(); NEXT; }
1048 CASE(50) { int c = ld_R_R<D,B,0>(); NEXT; }
1049 CASE(51) { int c = ld_R_R<D,C,0>(); NEXT; }
1050 CASE(53) { int c = ld_R_R<D,E,0>(); NEXT; }
1051 CASE(54) { int c = ld_R_R<D,H,0>(); NEXT; }
1052 CASE(55) { int c = ld_R_R<D,L,0>(); NEXT; }
1053 CASE(57) { int c = ld_R_R<D,A,0>(); NEXT; }
1054 CASE(58) { int c = ld_R_R<E,B,0>(); NEXT; }
1055 CASE(59) { int c = ld_R_R<E,C,0>(); NEXT; }
1056 CASE(5A) { int c = ld_R_R<E,D,0>(); NEXT; }
1057 CASE(5C) { int c = ld_R_R<E,H,0>(); NEXT; }
1058 CASE(5D) { int c = ld_R_R<E,L,0>(); NEXT; }
1059 CASE(5F) { int c = ld_R_R<E,A,0>(); NEXT; }
1060 CASE(60) { int c = ld_R_R<H,B,0>(); NEXT; }
1061 CASE(61) { int c = ld_R_R<H,C,0>(); NEXT; }
1062 CASE(62) { int c = ld_R_R<H,D,0>(); NEXT; }
1063 CASE(63) { int c = ld_R_R<H,E,0>(); NEXT; }
1064 CASE(65) { int c = ld_R_R<H,L,0>(); NEXT; }
1065 CASE(67) { int c = ld_R_R<H,A,0>(); NEXT; }
1066 CASE(68) { int c = ld_R_R<L,B,0>(); NEXT; }
1067 CASE(69) { int c = ld_R_R<L,C,0>(); NEXT; }
1068 CASE(6A) { int c = ld_R_R<L,D,0>(); NEXT; }
1069 CASE(6B) { int c = ld_R_R<L,E,0>(); NEXT; }
1070 CASE(6C) { int c = ld_R_R<L,H,0>(); NEXT; }
1071 CASE(6F) { int c = ld_R_R<L,A,0>(); NEXT; }
1072 CASE(78) { int c = ld_R_R<A,B,0>(); NEXT; }
1073 CASE(79) { int c = ld_R_R<A,C,0>(); NEXT; }
1074 CASE(7A) { int c = ld_R_R<A,D,0>(); NEXT; }
1075 CASE(7B) { int c = ld_R_R<A,E,0>(); NEXT; }
1076 CASE(7C) { int c = ld_R_R<A,H,0>(); NEXT; }
1077 CASE(7D) { int c = ld_R_R<A,L,0>(); NEXT; }
1078 CASE(70) { int c = ld_xhl_R<B>(); NEXT; }
1079 CASE(71) { int c = ld_xhl_R<C>(); NEXT; }
1080 CASE(72) { int c = ld_xhl_R<D>(); NEXT; }
1081 CASE(73) { int c = ld_xhl_R<E>(); NEXT; }
1082 CASE(74) { int c = ld_xhl_R<H>(); NEXT; }
1083 CASE(75) { int c = ld_xhl_R<L>(); NEXT; }
1084 CASE(77) { int c = ld_xhl_R<A>(); NEXT; }
1085 CASE(46) { int c = ld_R_xhl<B>(); NEXT; }
1086 CASE(4E) { int c = ld_R_xhl<C>(); NEXT; }
1087 CASE(56) { int c = ld_R_xhl<D>(); NEXT; }
1088 CASE(5E) { int c = ld_R_xhl<E>(); NEXT; }
1089 CASE(66) { int c = ld_R_xhl<H>(); NEXT; }
1090 CASE(6E) { int c = ld_R_xhl<L>(); NEXT; }
1091 CASE(7E) { int c = ld_R_xhl<A>(); NEXT; }
1092 CASE(76) { int c = halt(); NEXT_STOP; }
1093 
1094 CASE(80) { int c = add_a_R<B,0>(); NEXT; }
1095 CASE(81) { int c = add_a_R<C,0>(); NEXT; }
1096 CASE(82) { int c = add_a_R<D,0>(); NEXT; }
1097 CASE(83) { int c = add_a_R<E,0>(); NEXT; }
1098 CASE(84) { int c = add_a_R<H,0>(); NEXT; }
1099 CASE(85) { int c = add_a_R<L,0>(); NEXT; }
1100 CASE(86) { int c = add_a_xhl(); NEXT; }
1101 CASE(87) { int c = add_a_a(); NEXT; }
1102 CASE(88) { int c = adc_a_R<B,0>(); NEXT; }
1103 CASE(89) { int c = adc_a_R<C,0>(); NEXT; }
1104 CASE(8A) { int c = adc_a_R<D,0>(); NEXT; }
1105 CASE(8B) { int c = adc_a_R<E,0>(); NEXT; }
1106 CASE(8C) { int c = adc_a_R<H,0>(); NEXT; }
1107 CASE(8D) { int c = adc_a_R<L,0>(); NEXT; }
1108 CASE(8E) { int c = adc_a_xhl(); NEXT; }
1109 CASE(8F) { int c = adc_a_a(); NEXT; }
1110 CASE(90) { int c = sub_R<B,0>(); NEXT; }
1111 CASE(91) { int c = sub_R<C,0>(); NEXT; }
1112 CASE(92) { int c = sub_R<D,0>(); NEXT; }
1113 CASE(93) { int c = sub_R<E,0>(); NEXT; }
1114 CASE(94) { int c = sub_R<H,0>(); NEXT; }
1115 CASE(95) { int c = sub_R<L,0>(); NEXT; }
1116 CASE(96) { int c = sub_xhl(); NEXT; }
1117 CASE(97) { int c = sub_a(); NEXT; }
1118 CASE(98) { int c = sbc_a_R<B,0>(); NEXT; }
1119 CASE(99) { int c = sbc_a_R<C,0>(); NEXT; }
1120 CASE(9A) { int c = sbc_a_R<D,0>(); NEXT; }
1121 CASE(9B) { int c = sbc_a_R<E,0>(); NEXT; }
1122 CASE(9C) { int c = sbc_a_R<H,0>(); NEXT; }
1123 CASE(9D) { int c = sbc_a_R<L,0>(); NEXT; }
1124 CASE(9E) { int c = sbc_a_xhl(); NEXT; }
1125 CASE(9F) { int c = sbc_a_a(); NEXT; }
1126 CASE(A0) { int c = and_R<B,0>(); NEXT; }
1127 CASE(A1) { int c = and_R<C,0>(); NEXT; }
1128 CASE(A2) { int c = and_R<D,0>(); NEXT; }
1129 CASE(A3) { int c = and_R<E,0>(); NEXT; }
1130 CASE(A4) { int c = and_R<H,0>(); NEXT; }
1131 CASE(A5) { int c = and_R<L,0>(); NEXT; }
1132 CASE(A6) { int c = and_xhl(); NEXT; }
1133 CASE(A7) { int c = and_a(); NEXT; }
1134 CASE(A8) { int c = xor_R<B,0>(); NEXT; }
1135 CASE(A9) { int c = xor_R<C,0>(); NEXT; }
1136 CASE(AA) { int c = xor_R<D,0>(); NEXT; }
1137 CASE(AB) { int c = xor_R<E,0>(); NEXT; }
1138 CASE(AC) { int c = xor_R<H,0>(); NEXT; }
1139 CASE(AD) { int c = xor_R<L,0>(); NEXT; }
1140 CASE(AE) { int c = xor_xhl(); NEXT; }
1141 CASE(AF) { int c = xor_a(); NEXT; }
1142 CASE(B0) { int c = or_R<B,0>(); NEXT; }
1143 CASE(B1) { int c = or_R<C,0>(); NEXT; }
1144 CASE(B2) { int c = or_R<D,0>(); NEXT; }
1145 CASE(B3) { int c = or_R<E,0>(); NEXT; }
1146 CASE(B4) { int c = or_R<H,0>(); NEXT; }
1147 CASE(B5) { int c = or_R<L,0>(); NEXT; }
1148 CASE(B6) { int c = or_xhl(); NEXT; }
1149 CASE(B7) { int c = or_a(); NEXT; }
1150 CASE(B8) { int c = cp_R<B,0>(); NEXT; }
1151 CASE(B9) { int c = cp_R<C,0>(); NEXT; }
1152 CASE(BA) { int c = cp_R<D,0>(); NEXT; }
1153 CASE(BB) { int c = cp_R<E,0>(); NEXT; }
1154 CASE(BC) { int c = cp_R<H,0>(); NEXT; }
1155 CASE(BD) { int c = cp_R<L,0>(); NEXT; }
1156 CASE(BE) { int c = cp_xhl(); NEXT; }
1157 CASE(BF) { int c = cp_a(); NEXT; }
1158 
1159 CASE(D3) { int c = out_byte_a(); NEXT; }
1160 CASE(DB) { int c = in_a_byte(); NEXT; }
1161 CASE(D9) { int c = exx(); NEXT; }
1162 CASE(E3) { int c = ex_xsp_SS<HL,0>(); NEXT; }
1163 CASE(EB) { int c = ex_de_hl(); NEXT; }
1164 CASE(E9) { int c = jp_SS<HL,0>(); NEXT; }
1165 CASE(F9) { int c = ld_sp_SS<HL,0>(); NEXT; }
1166 CASE(F3) { int c = di(); NEXT; }
1167 CASE(FB) { int c = ei(); NEXT_EI; }
1168 CASE(C6) { int c = add_a_byte(); NEXT; }
1169 CASE(CE) { int c = adc_a_byte(); NEXT; }
1170 CASE(D6) { int c = sub_byte(); NEXT; }
1171 CASE(DE) { int c = sbc_a_byte(); NEXT; }
1172 CASE(E6) { int c = and_byte(); NEXT; }
1173 CASE(EE) { int c = xor_byte(); NEXT; }
1174 CASE(F6) { int c = or_byte(); NEXT; }
1175 CASE(FE) { int c = cp_byte(); NEXT; }
1176 CASE(C0) { int c = ret(CondNZ()); NEXT; }
1177 CASE(C8) { int c = ret(CondZ ()); NEXT; }
1178 CASE(D0) { int c = ret(CondNC()); NEXT; }
1179 CASE(D8) { int c = ret(CondC ()); NEXT; }
1180 CASE(E0) { int c = ret(CondPO()); NEXT; }
1181 CASE(E8) { int c = ret(CondPE()); NEXT; }
1182 CASE(F0) { int c = ret(CondP ()); NEXT; }
1183 CASE(F8) { int c = ret(CondM ()); NEXT; }
1184 CASE(C9) { int c = ret(); NEXT; }
1185 CASE(C2) { int c = jp(CondNZ()); NEXT; }
1186 CASE(CA) { int c = jp(CondZ ()); NEXT; }
1187 CASE(D2) { int c = jp(CondNC()); NEXT; }
1188 CASE(DA) { int c = jp(CondC ()); NEXT; }
1189 CASE(E2) { int c = jp(CondPO()); NEXT; }
1190 CASE(EA) { int c = jp(CondPE()); NEXT; }
1191 CASE(F2) { int c = jp(CondP ()); NEXT; }
1192 CASE(FA) { int c = jp(CondM ()); NEXT; }
1193 CASE(C3) { int c = jp(CondTrue()); NEXT; }
1194 CASE(C4) { int c = call(CondNZ()); NEXT; }
1195 CASE(CC) { int c = call(CondZ ()); NEXT; }
1196 CASE(D4) { int c = call(CondNC()); NEXT; }
1197 CASE(DC) { int c = call(CondC ()); NEXT; }
1198 CASE(E4) { int c = call(CondPO()); NEXT; }
1199 CASE(EC) { int c = call(CondPE()); NEXT; }
1200 CASE(F4) { int c = call(CondP ()); NEXT; }
1201 CASE(FC) { int c = call(CondM ()); NEXT; }
1202 CASE(CD) { int c = call(CondTrue()); NEXT; }
1203 CASE(C1) { int c = pop_SS <BC,0>(); NEXT; }
1204 CASE(D1) { int c = pop_SS <DE,0>(); NEXT; }
1205 CASE(E1) { int c = pop_SS <HL,0>(); NEXT; }
1206 CASE(F1) { int c = pop_SS <AF,0>(); NEXT; }
1207 CASE(C5) { int c = push_SS<BC,0>(); NEXT; }
1208 CASE(D5) { int c = push_SS<DE,0>(); NEXT; }
1209 CASE(E5) { int c = push_SS<HL,0>(); NEXT; }
1210 CASE(F5) { int c = push_SS<AF,0>(); NEXT; }
1211 CASE(C7) { int c = rst<0x00>(); NEXT; }
1212 CASE(CF) { int c = rst<0x08>(); NEXT; }
1213 CASE(D7) { int c = rst<0x10>(); NEXT; }
1214 CASE(DF) { int c = rst<0x18>(); NEXT; }
1215 CASE(E7) { int c = rst<0x20>(); NEXT; }
1216 CASE(EF) { int c = rst<0x28>(); NEXT; }
1217 CASE(F7) { int c = rst<0x30>(); NEXT; }
1218 CASE(FF) { int c = rst<0x38>(); NEXT; }
1219 CASE(CB) {
1220  byte cb_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1221  incR(1);
1222  switch (cb_opcode) {
1223  case 0x00: { int c = rlc_R<B>(); NEXT; }
1224  case 0x01: { int c = rlc_R<C>(); NEXT; }
1225  case 0x02: { int c = rlc_R<D>(); NEXT; }
1226  case 0x03: { int c = rlc_R<E>(); NEXT; }
1227  case 0x04: { int c = rlc_R<H>(); NEXT; }
1228  case 0x05: { int c = rlc_R<L>(); NEXT; }
1229  case 0x07: { int c = rlc_R<A>(); NEXT; }
1230  case 0x06: { int c = rlc_xhl(); NEXT; }
1231  case 0x08: { int c = rrc_R<B>(); NEXT; }
1232  case 0x09: { int c = rrc_R<C>(); NEXT; }
1233  case 0x0a: { int c = rrc_R<D>(); NEXT; }
1234  case 0x0b: { int c = rrc_R<E>(); NEXT; }
1235  case 0x0c: { int c = rrc_R<H>(); NEXT; }
1236  case 0x0d: { int c = rrc_R<L>(); NEXT; }
1237  case 0x0f: { int c = rrc_R<A>(); NEXT; }
1238  case 0x0e: { int c = rrc_xhl(); NEXT; }
1239  case 0x10: { int c = rl_R<B>(); NEXT; }
1240  case 0x11: { int c = rl_R<C>(); NEXT; }
1241  case 0x12: { int c = rl_R<D>(); NEXT; }
1242  case 0x13: { int c = rl_R<E>(); NEXT; }
1243  case 0x14: { int c = rl_R<H>(); NEXT; }
1244  case 0x15: { int c = rl_R<L>(); NEXT; }
1245  case 0x17: { int c = rl_R<A>(); NEXT; }
1246  case 0x16: { int c = rl_xhl(); NEXT; }
1247  case 0x18: { int c = rr_R<B>(); NEXT; }
1248  case 0x19: { int c = rr_R<C>(); NEXT; }
1249  case 0x1a: { int c = rr_R<D>(); NEXT; }
1250  case 0x1b: { int c = rr_R<E>(); NEXT; }
1251  case 0x1c: { int c = rr_R<H>(); NEXT; }
1252  case 0x1d: { int c = rr_R<L>(); NEXT; }
1253  case 0x1f: { int c = rr_R<A>(); NEXT; }
1254  case 0x1e: { int c = rr_xhl(); NEXT; }
1255  case 0x20: { int c = sla_R<B>(); NEXT; }
1256  case 0x21: { int c = sla_R<C>(); NEXT; }
1257  case 0x22: { int c = sla_R<D>(); NEXT; }
1258  case 0x23: { int c = sla_R<E>(); NEXT; }
1259  case 0x24: { int c = sla_R<H>(); NEXT; }
1260  case 0x25: { int c = sla_R<L>(); NEXT; }
1261  case 0x27: { int c = sla_R<A>(); NEXT; }
1262  case 0x26: { int c = sla_xhl(); NEXT; }
1263  case 0x28: { int c = sra_R<B>(); NEXT; }
1264  case 0x29: { int c = sra_R<C>(); NEXT; }
1265  case 0x2a: { int c = sra_R<D>(); NEXT; }
1266  case 0x2b: { int c = sra_R<E>(); NEXT; }
1267  case 0x2c: { int c = sra_R<H>(); NEXT; }
1268  case 0x2d: { int c = sra_R<L>(); NEXT; }
1269  case 0x2f: { int c = sra_R<A>(); NEXT; }
1270  case 0x2e: { int c = sra_xhl(); NEXT; }
1271  case 0x30: { int c = T::isR800() ? sla_R<B>() : sll_R<B>(); NEXT; }
1272  case 0x31: { int c = T::isR800() ? sla_R<C>() : sll_R<C>(); NEXT; }
1273  case 0x32: { int c = T::isR800() ? sla_R<D>() : sll_R<D>(); NEXT; }
1274  case 0x33: { int c = T::isR800() ? sla_R<E>() : sll_R<E>(); NEXT; }
1275  case 0x34: { int c = T::isR800() ? sla_R<H>() : sll_R<H>(); NEXT; }
1276  case 0x35: { int c = T::isR800() ? sla_R<L>() : sll_R<L>(); NEXT; }
1277  case 0x37: { int c = T::isR800() ? sla_R<A>() : sll_R<A>(); NEXT; }
1278  case 0x36: { int c = T::isR800() ? sla_xhl() : sll_xhl(); NEXT; }
1279  case 0x38: { int c = srl_R<B>(); NEXT; }
1280  case 0x39: { int c = srl_R<C>(); NEXT; }
1281  case 0x3a: { int c = srl_R<D>(); NEXT; }
1282  case 0x3b: { int c = srl_R<E>(); NEXT; }
1283  case 0x3c: { int c = srl_R<H>(); NEXT; }
1284  case 0x3d: { int c = srl_R<L>(); NEXT; }
1285  case 0x3f: { int c = srl_R<A>(); NEXT; }
1286  case 0x3e: { int c = srl_xhl(); NEXT; }
1287 
1288  case 0x40: { int c = bit_N_R<0,B>(); NEXT; }
1289  case 0x41: { int c = bit_N_R<0,C>(); NEXT; }
1290  case 0x42: { int c = bit_N_R<0,D>(); NEXT; }
1291  case 0x43: { int c = bit_N_R<0,E>(); NEXT; }
1292  case 0x44: { int c = bit_N_R<0,H>(); NEXT; }
1293  case 0x45: { int c = bit_N_R<0,L>(); NEXT; }
1294  case 0x47: { int c = bit_N_R<0,A>(); NEXT; }
1295  case 0x48: { int c = bit_N_R<1,B>(); NEXT; }
1296  case 0x49: { int c = bit_N_R<1,C>(); NEXT; }
1297  case 0x4a: { int c = bit_N_R<1,D>(); NEXT; }
1298  case 0x4b: { int c = bit_N_R<1,E>(); NEXT; }
1299  case 0x4c: { int c = bit_N_R<1,H>(); NEXT; }
1300  case 0x4d: { int c = bit_N_R<1,L>(); NEXT; }
1301  case 0x4f: { int c = bit_N_R<1,A>(); NEXT; }
1302  case 0x50: { int c = bit_N_R<2,B>(); NEXT; }
1303  case 0x51: { int c = bit_N_R<2,C>(); NEXT; }
1304  case 0x52: { int c = bit_N_R<2,D>(); NEXT; }
1305  case 0x53: { int c = bit_N_R<2,E>(); NEXT; }
1306  case 0x54: { int c = bit_N_R<2,H>(); NEXT; }
1307  case 0x55: { int c = bit_N_R<2,L>(); NEXT; }
1308  case 0x57: { int c = bit_N_R<2,A>(); NEXT; }
1309  case 0x58: { int c = bit_N_R<3,B>(); NEXT; }
1310  case 0x59: { int c = bit_N_R<3,C>(); NEXT; }
1311  case 0x5a: { int c = bit_N_R<3,D>(); NEXT; }
1312  case 0x5b: { int c = bit_N_R<3,E>(); NEXT; }
1313  case 0x5c: { int c = bit_N_R<3,H>(); NEXT; }
1314  case 0x5d: { int c = bit_N_R<3,L>(); NEXT; }
1315  case 0x5f: { int c = bit_N_R<3,A>(); NEXT; }
1316  case 0x60: { int c = bit_N_R<4,B>(); NEXT; }
1317  case 0x61: { int c = bit_N_R<4,C>(); NEXT; }
1318  case 0x62: { int c = bit_N_R<4,D>(); NEXT; }
1319  case 0x63: { int c = bit_N_R<4,E>(); NEXT; }
1320  case 0x64: { int c = bit_N_R<4,H>(); NEXT; }
1321  case 0x65: { int c = bit_N_R<4,L>(); NEXT; }
1322  case 0x67: { int c = bit_N_R<4,A>(); NEXT; }
1323  case 0x68: { int c = bit_N_R<5,B>(); NEXT; }
1324  case 0x69: { int c = bit_N_R<5,C>(); NEXT; }
1325  case 0x6a: { int c = bit_N_R<5,D>(); NEXT; }
1326  case 0x6b: { int c = bit_N_R<5,E>(); NEXT; }
1327  case 0x6c: { int c = bit_N_R<5,H>(); NEXT; }
1328  case 0x6d: { int c = bit_N_R<5,L>(); NEXT; }
1329  case 0x6f: { int c = bit_N_R<5,A>(); NEXT; }
1330  case 0x70: { int c = bit_N_R<6,B>(); NEXT; }
1331  case 0x71: { int c = bit_N_R<6,C>(); NEXT; }
1332  case 0x72: { int c = bit_N_R<6,D>(); NEXT; }
1333  case 0x73: { int c = bit_N_R<6,E>(); NEXT; }
1334  case 0x74: { int c = bit_N_R<6,H>(); NEXT; }
1335  case 0x75: { int c = bit_N_R<6,L>(); NEXT; }
1336  case 0x77: { int c = bit_N_R<6,A>(); NEXT; }
1337  case 0x78: { int c = bit_N_R<7,B>(); NEXT; }
1338  case 0x79: { int c = bit_N_R<7,C>(); NEXT; }
1339  case 0x7a: { int c = bit_N_R<7,D>(); NEXT; }
1340  case 0x7b: { int c = bit_N_R<7,E>(); NEXT; }
1341  case 0x7c: { int c = bit_N_R<7,H>(); NEXT; }
1342  case 0x7d: { int c = bit_N_R<7,L>(); NEXT; }
1343  case 0x7f: { int c = bit_N_R<7,A>(); NEXT; }
1344  case 0x46: { int c = bit_N_xhl<0>(); NEXT; }
1345  case 0x4e: { int c = bit_N_xhl<1>(); NEXT; }
1346  case 0x56: { int c = bit_N_xhl<2>(); NEXT; }
1347  case 0x5e: { int c = bit_N_xhl<3>(); NEXT; }
1348  case 0x66: { int c = bit_N_xhl<4>(); NEXT; }
1349  case 0x6e: { int c = bit_N_xhl<5>(); NEXT; }
1350  case 0x76: { int c = bit_N_xhl<6>(); NEXT; }
1351  case 0x7e: { int c = bit_N_xhl<7>(); NEXT; }
1352 
1353  case 0x80: { int c = res_N_R<0,B>(); NEXT; }
1354  case 0x81: { int c = res_N_R<0,C>(); NEXT; }
1355  case 0x82: { int c = res_N_R<0,D>(); NEXT; }
1356  case 0x83: { int c = res_N_R<0,E>(); NEXT; }
1357  case 0x84: { int c = res_N_R<0,H>(); NEXT; }
1358  case 0x85: { int c = res_N_R<0,L>(); NEXT; }
1359  case 0x87: { int c = res_N_R<0,A>(); NEXT; }
1360  case 0x88: { int c = res_N_R<1,B>(); NEXT; }
1361  case 0x89: { int c = res_N_R<1,C>(); NEXT; }
1362  case 0x8a: { int c = res_N_R<1,D>(); NEXT; }
1363  case 0x8b: { int c = res_N_R<1,E>(); NEXT; }
1364  case 0x8c: { int c = res_N_R<1,H>(); NEXT; }
1365  case 0x8d: { int c = res_N_R<1,L>(); NEXT; }
1366  case 0x8f: { int c = res_N_R<1,A>(); NEXT; }
1367  case 0x90: { int c = res_N_R<2,B>(); NEXT; }
1368  case 0x91: { int c = res_N_R<2,C>(); NEXT; }
1369  case 0x92: { int c = res_N_R<2,D>(); NEXT; }
1370  case 0x93: { int c = res_N_R<2,E>(); NEXT; }
1371  case 0x94: { int c = res_N_R<2,H>(); NEXT; }
1372  case 0x95: { int c = res_N_R<2,L>(); NEXT; }
1373  case 0x97: { int c = res_N_R<2,A>(); NEXT; }
1374  case 0x98: { int c = res_N_R<3,B>(); NEXT; }
1375  case 0x99: { int c = res_N_R<3,C>(); NEXT; }
1376  case 0x9a: { int c = res_N_R<3,D>(); NEXT; }
1377  case 0x9b: { int c = res_N_R<3,E>(); NEXT; }
1378  case 0x9c: { int c = res_N_R<3,H>(); NEXT; }
1379  case 0x9d: { int c = res_N_R<3,L>(); NEXT; }
1380  case 0x9f: { int c = res_N_R<3,A>(); NEXT; }
1381  case 0xa0: { int c = res_N_R<4,B>(); NEXT; }
1382  case 0xa1: { int c = res_N_R<4,C>(); NEXT; }
1383  case 0xa2: { int c = res_N_R<4,D>(); NEXT; }
1384  case 0xa3: { int c = res_N_R<4,E>(); NEXT; }
1385  case 0xa4: { int c = res_N_R<4,H>(); NEXT; }
1386  case 0xa5: { int c = res_N_R<4,L>(); NEXT; }
1387  case 0xa7: { int c = res_N_R<4,A>(); NEXT; }
1388  case 0xa8: { int c = res_N_R<5,B>(); NEXT; }
1389  case 0xa9: { int c = res_N_R<5,C>(); NEXT; }
1390  case 0xaa: { int c = res_N_R<5,D>(); NEXT; }
1391  case 0xab: { int c = res_N_R<5,E>(); NEXT; }
1392  case 0xac: { int c = res_N_R<5,H>(); NEXT; }
1393  case 0xad: { int c = res_N_R<5,L>(); NEXT; }
1394  case 0xaf: { int c = res_N_R<5,A>(); NEXT; }
1395  case 0xb0: { int c = res_N_R<6,B>(); NEXT; }
1396  case 0xb1: { int c = res_N_R<6,C>(); NEXT; }
1397  case 0xb2: { int c = res_N_R<6,D>(); NEXT; }
1398  case 0xb3: { int c = res_N_R<6,E>(); NEXT; }
1399  case 0xb4: { int c = res_N_R<6,H>(); NEXT; }
1400  case 0xb5: { int c = res_N_R<6,L>(); NEXT; }
1401  case 0xb7: { int c = res_N_R<6,A>(); NEXT; }
1402  case 0xb8: { int c = res_N_R<7,B>(); NEXT; }
1403  case 0xb9: { int c = res_N_R<7,C>(); NEXT; }
1404  case 0xba: { int c = res_N_R<7,D>(); NEXT; }
1405  case 0xbb: { int c = res_N_R<7,E>(); NEXT; }
1406  case 0xbc: { int c = res_N_R<7,H>(); NEXT; }
1407  case 0xbd: { int c = res_N_R<7,L>(); NEXT; }
1408  case 0xbf: { int c = res_N_R<7,A>(); NEXT; }
1409  case 0x86: { int c = res_N_xhl<0>(); NEXT; }
1410  case 0x8e: { int c = res_N_xhl<1>(); NEXT; }
1411  case 0x96: { int c = res_N_xhl<2>(); NEXT; }
1412  case 0x9e: { int c = res_N_xhl<3>(); NEXT; }
1413  case 0xa6: { int c = res_N_xhl<4>(); NEXT; }
1414  case 0xae: { int c = res_N_xhl<5>(); NEXT; }
1415  case 0xb6: { int c = res_N_xhl<6>(); NEXT; }
1416  case 0xbe: { int c = res_N_xhl<7>(); NEXT; }
1417 
1418  case 0xc0: { int c = set_N_R<0,B>(); NEXT; }
1419  case 0xc1: { int c = set_N_R<0,C>(); NEXT; }
1420  case 0xc2: { int c = set_N_R<0,D>(); NEXT; }
1421  case 0xc3: { int c = set_N_R<0,E>(); NEXT; }
1422  case 0xc4: { int c = set_N_R<0,H>(); NEXT; }
1423  case 0xc5: { int c = set_N_R<0,L>(); NEXT; }
1424  case 0xc7: { int c = set_N_R<0,A>(); NEXT; }
1425  case 0xc8: { int c = set_N_R<1,B>(); NEXT; }
1426  case 0xc9: { int c = set_N_R<1,C>(); NEXT; }
1427  case 0xca: { int c = set_N_R<1,D>(); NEXT; }
1428  case 0xcb: { int c = set_N_R<1,E>(); NEXT; }
1429  case 0xcc: { int c = set_N_R<1,H>(); NEXT; }
1430  case 0xcd: { int c = set_N_R<1,L>(); NEXT; }
1431  case 0xcf: { int c = set_N_R<1,A>(); NEXT; }
1432  case 0xd0: { int c = set_N_R<2,B>(); NEXT; }
1433  case 0xd1: { int c = set_N_R<2,C>(); NEXT; }
1434  case 0xd2: { int c = set_N_R<2,D>(); NEXT; }
1435  case 0xd3: { int c = set_N_R<2,E>(); NEXT; }
1436  case 0xd4: { int c = set_N_R<2,H>(); NEXT; }
1437  case 0xd5: { int c = set_N_R<2,L>(); NEXT; }
1438  case 0xd7: { int c = set_N_R<2,A>(); NEXT; }
1439  case 0xd8: { int c = set_N_R<3,B>(); NEXT; }
1440  case 0xd9: { int c = set_N_R<3,C>(); NEXT; }
1441  case 0xda: { int c = set_N_R<3,D>(); NEXT; }
1442  case 0xdb: { int c = set_N_R<3,E>(); NEXT; }
1443  case 0xdc: { int c = set_N_R<3,H>(); NEXT; }
1444  case 0xdd: { int c = set_N_R<3,L>(); NEXT; }
1445  case 0xdf: { int c = set_N_R<3,A>(); NEXT; }
1446  case 0xe0: { int c = set_N_R<4,B>(); NEXT; }
1447  case 0xe1: { int c = set_N_R<4,C>(); NEXT; }
1448  case 0xe2: { int c = set_N_R<4,D>(); NEXT; }
1449  case 0xe3: { int c = set_N_R<4,E>(); NEXT; }
1450  case 0xe4: { int c = set_N_R<4,H>(); NEXT; }
1451  case 0xe5: { int c = set_N_R<4,L>(); NEXT; }
1452  case 0xe7: { int c = set_N_R<4,A>(); NEXT; }
1453  case 0xe8: { int c = set_N_R<5,B>(); NEXT; }
1454  case 0xe9: { int c = set_N_R<5,C>(); NEXT; }
1455  case 0xea: { int c = set_N_R<5,D>(); NEXT; }
1456  case 0xeb: { int c = set_N_R<5,E>(); NEXT; }
1457  case 0xec: { int c = set_N_R<5,H>(); NEXT; }
1458  case 0xed: { int c = set_N_R<5,L>(); NEXT; }
1459  case 0xef: { int c = set_N_R<5,A>(); NEXT; }
1460  case 0xf0: { int c = set_N_R<6,B>(); NEXT; }
1461  case 0xf1: { int c = set_N_R<6,C>(); NEXT; }
1462  case 0xf2: { int c = set_N_R<6,D>(); NEXT; }
1463  case 0xf3: { int c = set_N_R<6,E>(); NEXT; }
1464  case 0xf4: { int c = set_N_R<6,H>(); NEXT; }
1465  case 0xf5: { int c = set_N_R<6,L>(); NEXT; }
1466  case 0xf7: { int c = set_N_R<6,A>(); NEXT; }
1467  case 0xf8: { int c = set_N_R<7,B>(); NEXT; }
1468  case 0xf9: { int c = set_N_R<7,C>(); NEXT; }
1469  case 0xfa: { int c = set_N_R<7,D>(); NEXT; }
1470  case 0xfb: { int c = set_N_R<7,E>(); NEXT; }
1471  case 0xfc: { int c = set_N_R<7,H>(); NEXT; }
1472  case 0xfd: { int c = set_N_R<7,L>(); NEXT; }
1473  case 0xff: { int c = set_N_R<7,A>(); NEXT; }
1474  case 0xc6: { int c = set_N_xhl<0>(); NEXT; }
1475  case 0xce: { int c = set_N_xhl<1>(); NEXT; }
1476  case 0xd6: { int c = set_N_xhl<2>(); NEXT; }
1477  case 0xde: { int c = set_N_xhl<3>(); NEXT; }
1478  case 0xe6: { int c = set_N_xhl<4>(); NEXT; }
1479  case 0xee: { int c = set_N_xhl<5>(); NEXT; }
1480  case 0xf6: { int c = set_N_xhl<6>(); NEXT; }
1481  case 0xfe: { int c = set_N_xhl<7>(); NEXT; }
1482  default: UNREACHABLE; return;
1483  }
1484 }
1485 CASE(ED) {
1486  byte ed_opcode = RDMEM_OPCODE(T::CC_PREFIX);
1487  incR(1);
1488  switch (ed_opcode) {
1489  case 0x00: case 0x01: case 0x02: case 0x03:
1490  case 0x04: case 0x05: case 0x06: case 0x07:
1491  case 0x08: case 0x09: case 0x0a: case 0x0b:
1492  case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1493  case 0x10: case 0x11: case 0x12: case 0x13:
1494  case 0x14: case 0x15: case 0x16: case 0x17:
1495  case 0x18: case 0x19: case 0x1a: case 0x1b:
1496  case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1497  case 0x20: case 0x21: case 0x22: case 0x23:
1498  case 0x24: case 0x25: case 0x26: case 0x27:
1499  case 0x28: case 0x29: case 0x2a: case 0x2b:
1500  case 0x2c: case 0x2d: case 0x2e: case 0x2f:
1501  case 0x30: case 0x31: case 0x32: case 0x33:
1502  case 0x34: case 0x35: case 0x36: case 0x37:
1503  case 0x38: case 0x39: case 0x3a: case 0x3b:
1504  case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1505 
1506  case 0x77: case 0x7f:
1507 
1508  case 0x80: case 0x81: case 0x82: case 0x83:
1509  case 0x84: case 0x85: case 0x86: case 0x87:
1510  case 0x88: case 0x89: case 0x8a: case 0x8b:
1511  case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1512  case 0x90: case 0x91: case 0x92: case 0x93:
1513  case 0x94: case 0x95: case 0x96: case 0x97:
1514  case 0x98: case 0x99: case 0x9a: case 0x9b:
1515  case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1516  case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1517  case 0xac: case 0xad: case 0xae: case 0xaf:
1518  case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1519  case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1520 
1521  case 0xc0: case 0xc2:
1522  case 0xc4: case 0xc5: case 0xc6: case 0xc7:
1523  case 0xc8: case 0xca: case 0xcb:
1524  case 0xcc: case 0xcd: case 0xce: case 0xcf:
1525  case 0xd0: case 0xd2: case 0xd3:
1526  case 0xd4: case 0xd5: case 0xd6: case 0xd7:
1527  case 0xd8: case 0xda: case 0xdb:
1528  case 0xdc: case 0xdd: case 0xde: case 0xdf:
1529  case 0xe0: case 0xe1: case 0xe2: case 0xe3:
1530  case 0xe4: case 0xe5: case 0xe6: case 0xe7:
1531  case 0xe8: case 0xe9: case 0xea: case 0xeb:
1532  case 0xec: case 0xed: case 0xee: case 0xef:
1533  case 0xf0: case 0xf1: case 0xf2:
1534  case 0xf4: case 0xf5: case 0xf6: case 0xf7:
1535  case 0xf8: case 0xf9: case 0xfa: case 0xfb:
1536  case 0xfc: case 0xfd: case 0xfe: case 0xff:
1537  { int c = nop(); NEXT; }
1538 
1539  case 0x40: { int c = in_R_c<B>(); NEXT; }
1540  case 0x48: { int c = in_R_c<C>(); NEXT; }
1541  case 0x50: { int c = in_R_c<D>(); NEXT; }
1542  case 0x58: { int c = in_R_c<E>(); NEXT; }
1543  case 0x60: { int c = in_R_c<H>(); NEXT; }
1544  case 0x68: { int c = in_R_c<L>(); NEXT; }
1545  case 0x70: { int c = in_R_c<DUMMY>(); NEXT; }
1546  case 0x78: { int c = in_R_c<A>(); NEXT; }
1547 
1548  case 0x41: { int c = out_c_R<B>(); NEXT; }
1549  case 0x49: { int c = out_c_R<C>(); NEXT; }
1550  case 0x51: { int c = out_c_R<D>(); NEXT; }
1551  case 0x59: { int c = out_c_R<E>(); NEXT; }
1552  case 0x61: { int c = out_c_R<H>(); NEXT; }
1553  case 0x69: { int c = out_c_R<L>(); NEXT; }
1554  case 0x71: { int c = out_c_0(); NEXT; }
1555  case 0x79: { int c = out_c_R<A>(); NEXT; }
1556 
1557  case 0x42: { int c = sbc_hl_SS<BC>(); NEXT; }
1558  case 0x52: { int c = sbc_hl_SS<DE>(); NEXT; }
1559  case 0x62: { int c = sbc_hl_hl (); NEXT; }
1560  case 0x72: { int c = sbc_hl_SS<SP>(); NEXT; }
1561 
1562  case 0x4a: { int c = adc_hl_SS<BC>(); NEXT; }
1563  case 0x5a: { int c = adc_hl_SS<DE>(); NEXT; }
1564  case 0x6a: { int c = adc_hl_hl (); NEXT; }
1565  case 0x7a: { int c = adc_hl_SS<SP>(); NEXT; }
1566 
1567  case 0x43: { int c = ld_xword_SS_ED<BC>(); NEXT; }
1568  case 0x53: { int c = ld_xword_SS_ED<DE>(); NEXT; }
1569  case 0x63: { int c = ld_xword_SS_ED<HL>(); NEXT; }
1570  case 0x73: { int c = ld_xword_SS_ED<SP>(); NEXT; }
1571 
1572  case 0x4b: { int c = ld_SS_xword_ED<BC>(); NEXT; }
1573  case 0x5b: { int c = ld_SS_xword_ED<DE>(); NEXT; }
1574  case 0x6b: { int c = ld_SS_xword_ED<HL>(); NEXT; }
1575  case 0x7b: { int c = ld_SS_xword_ED<SP>(); NEXT; }
1576 
1577  case 0x47: { int c = ld_i_a(); NEXT; }
1578  case 0x4f: { int c = ld_r_a(); NEXT; }
1579  case 0x57: { int c = ld_a_IR<REG_I>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1580  case 0x5f: { int c = ld_a_IR<REG_R>(); if (T::isR800()) { NEXT; } else { NEXT_STOP; }}
1581 
1582  case 0x67: { int c = rrd(); NEXT; }
1583  case 0x6f: { int c = rld(); NEXT; }
1584 
1585  case 0x45: case 0x4d: case 0x55: case 0x5d:
1586  case 0x65: case 0x6d: case 0x75: case 0x7d:
1587  { int c = retn(); NEXT_STOP; }
1588  case 0x46: case 0x4e: case 0x66: case 0x6e:
1589  { int c = im_N<0>(); NEXT; }
1590  case 0x56: case 0x76:
1591  { int c = im_N<1>(); NEXT; }
1592  case 0x5e: case 0x7e:
1593  { int c = im_N<2>(); NEXT; }
1594  case 0x44: case 0x4c: case 0x54: case 0x5c:
1595  case 0x64: case 0x6c: case 0x74: case 0x7c:
1596  { int c = neg(); NEXT; }
1597 
1598  case 0xa0: { int c = ldi(); NEXT; }
1599  case 0xa1: { int c = cpi(); NEXT; }
1600  case 0xa2: { int c = ini(); NEXT; }
1601  case 0xa3: { int c = outi(); NEXT; }
1602  case 0xa8: { int c = ldd(); NEXT; }
1603  case 0xa9: { int c = cpd(); NEXT; }
1604  case 0xaa: { int c = ind(); NEXT; }
1605  case 0xab: { int c = outd(); NEXT; }
1606  case 0xb0: { int c = ldir(); NEXT; }
1607  case 0xb1: { int c = cpir(); NEXT; }
1608  case 0xb2: { int c = inir(); NEXT; }
1609  case 0xb3: { int c = otir(); NEXT; }
1610  case 0xb8: { int c = lddr(); NEXT; }
1611  case 0xb9: { int c = cpdr(); NEXT; }
1612  case 0xba: { int c = indr(); NEXT; }
1613  case 0xbb: { int c = otdr(); NEXT; }
1614 
1615  case 0xc1: { int c = T::isR800() ? mulub_a_R<B>() : nop(); NEXT; }
1616  case 0xc9: { int c = T::isR800() ? mulub_a_R<C>() : nop(); NEXT; }
1617  case 0xd1: { int c = T::isR800() ? mulub_a_R<D>() : nop(); NEXT; }
1618  case 0xd9: { int c = T::isR800() ? mulub_a_R<E>() : nop(); NEXT; }
1619  case 0xc3: { int c = T::isR800() ? muluw_hl_SS<BC>() : nop(); NEXT; }
1620  case 0xf3: { int c = T::isR800() ? muluw_hl_SS<SP>() : nop(); NEXT; }
1621  default: UNREACHABLE; return;
1622  }
1623 }
1624 opDD_2:
1625 CASE(DD) {
1626  byte opcodeDD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1627  incR(1);
1628  switch (opcodeDD) {
1629  case 0x00: // nop();
1630  case 0x01: // ld_bc_word();
1631  case 0x02: // ld_xbc_a();
1632  case 0x03: // inc_bc();
1633  case 0x04: // inc_b();
1634  case 0x05: // dec_b();
1635  case 0x06: // ld_b_byte();
1636  case 0x07: // rlca();
1637  case 0x08: // ex_af_af();
1638  case 0x0a: // ld_a_xbc();
1639  case 0x0b: // dec_bc();
1640  case 0x0c: // inc_c();
1641  case 0x0d: // dec_c();
1642  case 0x0e: // ld_c_byte();
1643  case 0x0f: // rrca();
1644  case 0x10: // djnz();
1645  case 0x11: // ld_de_word();
1646  case 0x12: // ld_xde_a();
1647  case 0x13: // inc_de();
1648  case 0x14: // inc_d();
1649  case 0x15: // dec_d();
1650  case 0x16: // ld_d_byte();
1651  case 0x17: // rla();
1652  case 0x18: // jr();
1653  case 0x1a: // ld_a_xde();
1654  case 0x1b: // dec_de();
1655  case 0x1c: // inc_e();
1656  case 0x1d: // dec_e();
1657  case 0x1e: // ld_e_byte();
1658  case 0x1f: // rra();
1659  case 0x20: // jr_nz();
1660  case 0x27: // daa();
1661  case 0x28: // jr_z();
1662  case 0x2f: // cpl();
1663  case 0x30: // jr_nc();
1664  case 0x31: // ld_sp_word();
1665  case 0x32: // ld_xbyte_a();
1666  case 0x33: // inc_sp();
1667  case 0x37: // scf();
1668  case 0x38: // jr_c();
1669  case 0x3a: // ld_a_xbyte();
1670  case 0x3b: // dec_sp();
1671  case 0x3c: // inc_a();
1672  case 0x3d: // dec_a();
1673  case 0x3e: // ld_a_byte();
1674  case 0x3f: // ccf();
1675 
1676  case 0x40: // ld_b_b();
1677  case 0x41: // ld_b_c();
1678  case 0x42: // ld_b_d();
1679  case 0x43: // ld_b_e();
1680  case 0x47: // ld_b_a();
1681  case 0x48: // ld_c_b();
1682  case 0x49: // ld_c_c();
1683  case 0x4a: // ld_c_d();
1684  case 0x4b: // ld_c_e();
1685  case 0x4f: // ld_c_a();
1686  case 0x50: // ld_d_b();
1687  case 0x51: // ld_d_c();
1688  case 0x52: // ld_d_d();
1689  case 0x53: // ld_d_e();
1690  case 0x57: // ld_d_a();
1691  case 0x58: // ld_e_b();
1692  case 0x59: // ld_e_c();
1693  case 0x5a: // ld_e_d();
1694  case 0x5b: // ld_e_e();
1695  case 0x5f: // ld_e_a();
1696  case 0x64: // ld_ixh_ixh(); == nop
1697  case 0x6d: // ld_ixl_ixl(); == nop
1698  case 0x76: // halt();
1699  case 0x78: // ld_a_b();
1700  case 0x79: // ld_a_c();
1701  case 0x7a: // ld_a_d();
1702  case 0x7b: // ld_a_e();
1703  case 0x7f: // ld_a_a();
1704 
1705  case 0x80: // add_a_b();
1706  case 0x81: // add_a_c();
1707  case 0x82: // add_a_d();
1708  case 0x83: // add_a_e();
1709  case 0x87: // add_a_a();
1710  case 0x88: // adc_a_b();
1711  case 0x89: // adc_a_c();
1712  case 0x8a: // adc_a_d();
1713  case 0x8b: // adc_a_e();
1714  case 0x8f: // adc_a_a();
1715  case 0x90: // sub_b();
1716  case 0x91: // sub_c();
1717  case 0x92: // sub_d();
1718  case 0x93: // sub_e();
1719  case 0x97: // sub_a();
1720  case 0x98: // sbc_a_b();
1721  case 0x99: // sbc_a_c();
1722  case 0x9a: // sbc_a_d();
1723  case 0x9b: // sbc_a_e();
1724  case 0x9f: // sbc_a_a();
1725  case 0xa0: // and_b();
1726  case 0xa1: // and_c();
1727  case 0xa2: // and_d();
1728  case 0xa3: // and_e();
1729  case 0xa7: // and_a();
1730  case 0xa8: // xor_b();
1731  case 0xa9: // xor_c();
1732  case 0xaa: // xor_d();
1733  case 0xab: // xor_e();
1734  case 0xaf: // xor_a();
1735  case 0xb0: // or_b();
1736  case 0xb1: // or_c();
1737  case 0xb2: // or_d();
1738  case 0xb3: // or_e();
1739  case 0xb7: // or_a();
1740  case 0xb8: // cp_b();
1741  case 0xb9: // cp_c();
1742  case 0xba: // cp_d();
1743  case 0xbb: // cp_e();
1744  case 0xbf: // cp_a();
1745 
1746  case 0xc0: // ret_nz();
1747  case 0xc1: // pop_bc();
1748  case 0xc2: // jp_nz();
1749  case 0xc3: // jp();
1750  case 0xc4: // call_nz();
1751  case 0xc5: // push_bc();
1752  case 0xc6: // add_a_byte();
1753  case 0xc7: // rst_00();
1754  case 0xc8: // ret_z();
1755  case 0xc9: // ret();
1756  case 0xca: // jp_z();
1757  case 0xcc: // call_z();
1758  case 0xcd: // call();
1759  case 0xce: // adc_a_byte();
1760  case 0xcf: // rst_08();
1761  case 0xd0: // ret_nc();
1762  case 0xd1: // pop_de();
1763  case 0xd2: // jp_nc();
1764  case 0xd3: // out_byte_a();
1765  case 0xd4: // call_nc();
1766  case 0xd5: // push_de();
1767  case 0xd6: // sub_byte();
1768  case 0xd7: // rst_10();
1769  case 0xd8: // ret_c();
1770  case 0xd9: // exx();
1771  case 0xda: // jp_c();
1772  case 0xdb: // in_a_byte();
1773  case 0xdc: // call_c();
1774  case 0xde: // sbc_a_byte();
1775  case 0xdf: // rst_18();
1776  case 0xe0: // ret_po();
1777  case 0xe2: // jp_po();
1778  case 0xe4: // call_po();
1779  case 0xe6: // and_byte();
1780  case 0xe7: // rst_20();
1781  case 0xe8: // ret_pe();
1782  case 0xea: // jp_pe();
1783  case 0xeb: // ex_de_hl();
1784  case 0xec: // call_pe();
1785  case 0xed: // ed();
1786  case 0xee: // xor_byte();
1787  case 0xef: // rst_28();
1788  case 0xf0: // ret_p();
1789  case 0xf1: // pop_af();
1790  case 0xf2: // jp_p();
1791  case 0xf3: // di();
1792  case 0xf4: // call_p();
1793  case 0xf5: // push_af();
1794  case 0xf6: // or_byte();
1795  case 0xf7: // rst_30();
1796  case 0xf8: // ret_m();
1797  case 0xfa: // jp_m();
1798  case 0xfb: // ei();
1799  case 0xfc: // call_m();
1800  case 0xfe: // cp_byte();
1801  case 0xff: // rst_38();
1802  if (T::isR800()) {
1803  int c = T::CC_DD + nop(); NEXT;
1804  } else {
1805  T::add(T::CC_DD);
1806  #ifdef USE_COMPUTED_GOTO
1807  goto *(opcodeTable[opcodeDD]);
1808  #else
1809  opcodeMain = opcodeDD;
1810  goto switchopcode;
1811  #endif
1812  }
1813 
1814  case 0x09: { int c = add_SS_TT<IX,BC,T::CC_DD>(); NEXT; }
1815  case 0x19: { int c = add_SS_TT<IX,DE,T::CC_DD>(); NEXT; }
1816  case 0x29: { int c = add_SS_SS<IX ,T::CC_DD>(); NEXT; }
1817  case 0x39: { int c = add_SS_TT<IX,SP,T::CC_DD>(); NEXT; }
1818  case 0x21: { int c = ld_SS_word<IX,T::CC_DD>(); NEXT; }
1819  case 0x22: { int c = ld_xword_SS<IX,T::CC_DD>(); NEXT; }
1820  case 0x2a: { int c = ld_SS_xword<IX,T::CC_DD>(); NEXT; }
1821  case 0x23: { int c = inc_SS<IX,T::CC_DD>(); NEXT; }
1822  case 0x2b: { int c = dec_SS<IX,T::CC_DD>(); NEXT; }
1823  case 0x24: { int c = inc_R<IXH,T::CC_DD>(); NEXT; }
1824  case 0x2c: { int c = inc_R<IXL,T::CC_DD>(); NEXT; }
1825  case 0x25: { int c = dec_R<IXH,T::CC_DD>(); NEXT; }
1826  case 0x2d: { int c = dec_R<IXL,T::CC_DD>(); NEXT; }
1827  case 0x26: { int c = ld_R_byte<IXH,T::CC_DD>(); NEXT; }
1828  case 0x2e: { int c = ld_R_byte<IXL,T::CC_DD>(); NEXT; }
1829  case 0x34: { int c = inc_xix<IX>(); NEXT; }
1830  case 0x35: { int c = dec_xix<IX>(); NEXT; }
1831  case 0x36: { int c = ld_xix_byte<IX>(); NEXT; }
1832 
1833  case 0x44: { int c = ld_R_R<B,IXH,T::CC_DD>(); NEXT; }
1834  case 0x45: { int c = ld_R_R<B,IXL,T::CC_DD>(); NEXT; }
1835  case 0x4c: { int c = ld_R_R<C,IXH,T::CC_DD>(); NEXT; }
1836  case 0x4d: { int c = ld_R_R<C,IXL,T::CC_DD>(); NEXT; }
1837  case 0x54: { int c = ld_R_R<D,IXH,T::CC_DD>(); NEXT; }
1838  case 0x55: { int c = ld_R_R<D,IXL,T::CC_DD>(); NEXT; }
1839  case 0x5c: { int c = ld_R_R<E,IXH,T::CC_DD>(); NEXT; }
1840  case 0x5d: { int c = ld_R_R<E,IXL,T::CC_DD>(); NEXT; }
1841  case 0x7c: { int c = ld_R_R<A,IXH,T::CC_DD>(); NEXT; }
1842  case 0x7d: { int c = ld_R_R<A,IXL,T::CC_DD>(); NEXT; }
1843  case 0x60: { int c = ld_R_R<IXH,B,T::CC_DD>(); NEXT; }
1844  case 0x61: { int c = ld_R_R<IXH,C,T::CC_DD>(); NEXT; }
1845  case 0x62: { int c = ld_R_R<IXH,D,T::CC_DD>(); NEXT; }
1846  case 0x63: { int c = ld_R_R<IXH,E,T::CC_DD>(); NEXT; }
1847  case 0x65: { int c = ld_R_R<IXH,IXL,T::CC_DD>(); NEXT; }
1848  case 0x67: { int c = ld_R_R<IXH,A,T::CC_DD>(); NEXT; }
1849  case 0x68: { int c = ld_R_R<IXL,B,T::CC_DD>(); NEXT; }
1850  case 0x69: { int c = ld_R_R<IXL,C,T::CC_DD>(); NEXT; }
1851  case 0x6a: { int c = ld_R_R<IXL,D,T::CC_DD>(); NEXT; }
1852  case 0x6b: { int c = ld_R_R<IXL,E,T::CC_DD>(); NEXT; }
1853  case 0x6c: { int c = ld_R_R<IXL,IXH,T::CC_DD>(); NEXT; }
1854  case 0x6f: { int c = ld_R_R<IXL,A,T::CC_DD>(); NEXT; }
1855  case 0x70: { int c = ld_xix_R<IX,B>(); NEXT; }
1856  case 0x71: { int c = ld_xix_R<IX,C>(); NEXT; }
1857  case 0x72: { int c = ld_xix_R<IX,D>(); NEXT; }
1858  case 0x73: { int c = ld_xix_R<IX,E>(); NEXT; }
1859  case 0x74: { int c = ld_xix_R<IX,H>(); NEXT; }
1860  case 0x75: { int c = ld_xix_R<IX,L>(); NEXT; }
1861  case 0x77: { int c = ld_xix_R<IX,A>(); NEXT; }
1862  case 0x46: { int c = ld_R_xix<B,IX>(); NEXT; }
1863  case 0x4e: { int c = ld_R_xix<C,IX>(); NEXT; }
1864  case 0x56: { int c = ld_R_xix<D,IX>(); NEXT; }
1865  case 0x5e: { int c = ld_R_xix<E,IX>(); NEXT; }
1866  case 0x66: { int c = ld_R_xix<H,IX>(); NEXT; }
1867  case 0x6e: { int c = ld_R_xix<L,IX>(); NEXT; }
1868  case 0x7e: { int c = ld_R_xix<A,IX>(); NEXT; }
1869 
1870  case 0x84: { int c = add_a_R<IXH,T::CC_DD>(); NEXT; }
1871  case 0x85: { int c = add_a_R<IXL,T::CC_DD>(); NEXT; }
1872  case 0x86: { int c = add_a_xix<IX>(); NEXT; }
1873  case 0x8c: { int c = adc_a_R<IXH,T::CC_DD>(); NEXT; }
1874  case 0x8d: { int c = adc_a_R<IXL,T::CC_DD>(); NEXT; }
1875  case 0x8e: { int c = adc_a_xix<IX>(); NEXT; }
1876  case 0x94: { int c = sub_R<IXH,T::CC_DD>(); NEXT; }
1877  case 0x95: { int c = sub_R<IXL,T::CC_DD>(); NEXT; }
1878  case 0x96: { int c = sub_xix<IX>(); NEXT; }
1879  case 0x9c: { int c = sbc_a_R<IXH,T::CC_DD>(); NEXT; }
1880  case 0x9d: { int c = sbc_a_R<IXL,T::CC_DD>(); NEXT; }
1881  case 0x9e: { int c = sbc_a_xix<IX>(); NEXT; }
1882  case 0xa4: { int c = and_R<IXH,T::CC_DD>(); NEXT; }
1883  case 0xa5: { int c = and_R<IXL,T::CC_DD>(); NEXT; }
1884  case 0xa6: { int c = and_xix<IX>(); NEXT; }
1885  case 0xac: { int c = xor_R<IXH,T::CC_DD>(); NEXT; }
1886  case 0xad: { int c = xor_R<IXL,T::CC_DD>(); NEXT; }
1887  case 0xae: { int c = xor_xix<IX>(); NEXT; }
1888  case 0xb4: { int c = or_R<IXH,T::CC_DD>(); NEXT; }
1889  case 0xb5: { int c = or_R<IXL,T::CC_DD>(); NEXT; }
1890  case 0xb6: { int c = or_xix<IX>(); NEXT; }
1891  case 0xbc: { int c = cp_R<IXH,T::CC_DD>(); NEXT; }
1892  case 0xbd: { int c = cp_R<IXL,T::CC_DD>(); NEXT; }
1893  case 0xbe: { int c = cp_xix<IX>(); NEXT; }
1894 
1895  case 0xe1: { int c = pop_SS <IX,T::CC_DD>(); NEXT; }
1896  case 0xe5: { int c = push_SS<IX,T::CC_DD>(); NEXT; }
1897  case 0xe3: { int c = ex_xsp_SS<IX,T::CC_DD>(); NEXT; }
1898  case 0xe9: { int c = jp_SS<IX,T::CC_DD>(); NEXT; }
1899  case 0xf9: { int c = ld_sp_SS<IX,T::CC_DD>(); NEXT; }
1900  case 0xcb: ixy = getIX(); goto xx_cb;
1901  case 0xdd: T::add(T::CC_DD); goto opDD_2;
1902  case 0xfd: T::add(T::CC_DD); goto opFD_2;
1903  default: UNREACHABLE; return;
1904  }
1905 }
1906 opFD_2:
1907 CASE(FD) {
1908  byte opcodeFD = RDMEM_OPCODE(T::CC_DD + T::CC_MAIN);
1909  incR(1);
1910  switch (opcodeFD) {
1911  case 0x00: // nop();
1912  case 0x01: // ld_bc_word();
1913  case 0x02: // ld_xbc_a();
1914  case 0x03: // inc_bc();
1915  case 0x04: // inc_b();
1916  case 0x05: // dec_b();
1917  case 0x06: // ld_b_byte();
1918  case 0x07: // rlca();
1919  case 0x08: // ex_af_af();
1920  case 0x0a: // ld_a_xbc();
1921  case 0x0b: // dec_bc();
1922  case 0x0c: // inc_c();
1923  case 0x0d: // dec_c();
1924  case 0x0e: // ld_c_byte();
1925  case 0x0f: // rrca();
1926  case 0x10: // djnz();
1927  case 0x11: // ld_de_word();
1928  case 0x12: // ld_xde_a();
1929  case 0x13: // inc_de();
1930  case 0x14: // inc_d();
1931  case 0x15: // dec_d();
1932  case 0x16: // ld_d_byte();
1933  case 0x17: // rla();
1934  case 0x18: // jr();
1935  case 0x1a: // ld_a_xde();
1936  case 0x1b: // dec_de();
1937  case 0x1c: // inc_e();
1938  case 0x1d: // dec_e();
1939  case 0x1e: // ld_e_byte();
1940  case 0x1f: // rra();
1941  case 0x20: // jr_nz();
1942  case 0x27: // daa();
1943  case 0x28: // jr_z();
1944  case 0x2f: // cpl();
1945  case 0x30: // jr_nc();
1946  case 0x31: // ld_sp_word();
1947  case 0x32: // ld_xbyte_a();
1948  case 0x33: // inc_sp();
1949  case 0x37: // scf();
1950  case 0x38: // jr_c();
1951  case 0x3a: // ld_a_xbyte();
1952  case 0x3b: // dec_sp();
1953  case 0x3c: // inc_a();
1954  case 0x3d: // dec_a();
1955  case 0x3e: // ld_a_byte();
1956  case 0x3f: // ccf();
1957 
1958  case 0x40: // ld_b_b();
1959  case 0x41: // ld_b_c();
1960  case 0x42: // ld_b_d();
1961  case 0x43: // ld_b_e();
1962  case 0x47: // ld_b_a();
1963  case 0x48: // ld_c_b();
1964  case 0x49: // ld_c_c();
1965  case 0x4a: // ld_c_d();
1966  case 0x4b: // ld_c_e();
1967  case 0x4f: // ld_c_a();
1968  case 0x50: // ld_d_b();
1969  case 0x51: // ld_d_c();
1970  case 0x52: // ld_d_d();
1971  case 0x53: // ld_d_e();
1972  case 0x57: // ld_d_a();
1973  case 0x58: // ld_e_b();
1974  case 0x59: // ld_e_c();
1975  case 0x5a: // ld_e_d();
1976  case 0x5b: // ld_e_e();
1977  case 0x5f: // ld_e_a();
1978  case 0x64: // ld_ixh_ixh(); == nop
1979  case 0x6d: // ld_ixl_ixl(); == nop
1980  case 0x76: // halt();
1981  case 0x78: // ld_a_b();
1982  case 0x79: // ld_a_c();
1983  case 0x7a: // ld_a_d();
1984  case 0x7b: // ld_a_e();
1985  case 0x7f: // ld_a_a();
1986 
1987  case 0x80: // add_a_b();
1988  case 0x81: // add_a_c();
1989  case 0x82: // add_a_d();
1990  case 0x83: // add_a_e();
1991  case 0x87: // add_a_a();
1992  case 0x88: // adc_a_b();
1993  case 0x89: // adc_a_c();
1994  case 0x8a: // adc_a_d();
1995  case 0x8b: // adc_a_e();
1996  case 0x8f: // adc_a_a();
1997  case 0x90: // sub_b();
1998  case 0x91: // sub_c();
1999  case 0x92: // sub_d();
2000  case 0x93: // sub_e();
2001  case 0x97: // sub_a();
2002  case 0x98: // sbc_a_b();
2003  case 0x99: // sbc_a_c();
2004  case 0x9a: // sbc_a_d();
2005  case 0x9b: // sbc_a_e();
2006  case 0x9f: // sbc_a_a();
2007  case 0xa0: // and_b();
2008  case 0xa1: // and_c();
2009  case 0xa2: // and_d();
2010  case 0xa3: // and_e();
2011  case 0xa7: // and_a();
2012  case 0xa8: // xor_b();
2013  case 0xa9: // xor_c();
2014  case 0xaa: // xor_d();
2015  case 0xab: // xor_e();
2016  case 0xaf: // xor_a();
2017  case 0xb0: // or_b();
2018  case 0xb1: // or_c();
2019  case 0xb2: // or_d();
2020  case 0xb3: // or_e();
2021  case 0xb7: // or_a();
2022  case 0xb8: // cp_b();
2023  case 0xb9: // cp_c();
2024  case 0xba: // cp_d();
2025  case 0xbb: // cp_e();
2026  case 0xbf: // cp_a();
2027 
2028  case 0xc0: // ret_nz();
2029  case 0xc1: // pop_bc();
2030  case 0xc2: // jp_nz();
2031  case 0xc3: // jp();
2032  case 0xc4: // call_nz();
2033  case 0xc5: // push_bc();
2034  case 0xc6: // add_a_byte();
2035  case 0xc7: // rst_00();
2036  case 0xc8: // ret_z();
2037  case 0xc9: // ret();
2038  case 0xca: // jp_z();
2039  case 0xcc: // call_z();
2040  case 0xcd: // call();
2041  case 0xce: // adc_a_byte();
2042  case 0xcf: // rst_08();
2043  case 0xd0: // ret_nc();
2044  case 0xd1: // pop_de();
2045  case 0xd2: // jp_nc();
2046  case 0xd3: // out_byte_a();
2047  case 0xd4: // call_nc();
2048  case 0xd5: // push_de();
2049  case 0xd6: // sub_byte();
2050  case 0xd7: // rst_10();
2051  case 0xd8: // ret_c();
2052  case 0xd9: // exx();
2053  case 0xda: // jp_c();
2054  case 0xdb: // in_a_byte();
2055  case 0xdc: // call_c();
2056  case 0xde: // sbc_a_byte();
2057  case 0xdf: // rst_18();
2058  case 0xe0: // ret_po();
2059  case 0xe2: // jp_po();
2060  case 0xe4: // call_po();
2061  case 0xe6: // and_byte();
2062  case 0xe7: // rst_20();
2063  case 0xe8: // ret_pe();
2064  case 0xea: // jp_pe();
2065  case 0xeb: // ex_de_hl();
2066  case 0xec: // call_pe();
2067  case 0xed: // ed();
2068  case 0xee: // xor_byte();
2069  case 0xef: // rst_28();
2070  case 0xf0: // ret_p();
2071  case 0xf1: // pop_af();
2072  case 0xf2: // jp_p();
2073  case 0xf3: // di();
2074  case 0xf4: // call_p();
2075  case 0xf5: // push_af();
2076  case 0xf6: // or_byte();
2077  case 0xf7: // rst_30();
2078  case 0xf8: // ret_m();
2079  case 0xfa: // jp_m();
2080  case 0xfb: // ei();
2081  case 0xfc: // call_m();
2082  case 0xfe: // cp_byte();
2083  case 0xff: // rst_38();
2084  if (T::isR800()) {
2085  int c = T::CC_DD + nop(); NEXT;
2086  } else {
2087  T::add(T::CC_DD);
2088  #ifdef USE_COMPUTED_GOTO
2089  goto *(opcodeTable[opcodeFD]);
2090  #else
2091  opcodeMain = opcodeFD;
2092  goto switchopcode;
2093  #endif
2094  }
2095 
2096  case 0x09: { int c = add_SS_TT<IY,BC,T::CC_DD>(); NEXT; }
2097  case 0x19: { int c = add_SS_TT<IY,DE,T::CC_DD>(); NEXT; }
2098  case 0x29: { int c = add_SS_SS<IY ,T::CC_DD>(); NEXT; }
2099  case 0x39: { int c = add_SS_TT<IY,SP,T::CC_DD>(); NEXT; }
2100  case 0x21: { int c = ld_SS_word<IY,T::CC_DD>(); NEXT; }
2101  case 0x22: { int c = ld_xword_SS<IY,T::CC_DD>(); NEXT; }
2102  case 0x2a: { int c = ld_SS_xword<IY,T::CC_DD>(); NEXT; }
2103  case 0x23: { int c = inc_SS<IY,T::CC_DD>(); NEXT; }
2104  case 0x2b: { int c = dec_SS<IY,T::CC_DD>(); NEXT; }
2105  case 0x24: { int c = inc_R<IYH,T::CC_DD>(); NEXT; }
2106  case 0x2c: { int c = inc_R<IYL,T::CC_DD>(); NEXT; }
2107  case 0x25: { int c = dec_R<IYH,T::CC_DD>(); NEXT; }
2108  case 0x2d: { int c = dec_R<IYL,T::CC_DD>(); NEXT; }
2109  case 0x26: { int c = ld_R_byte<IYH,T::CC_DD>(); NEXT; }
2110  case 0x2e: { int c = ld_R_byte<IYL,T::CC_DD>(); NEXT; }
2111  case 0x34: { int c = inc_xix<IY>(); NEXT; }
2112  case 0x35: { int c = dec_xix<IY>(); NEXT; }
2113  case 0x36: { int c = ld_xix_byte<IY>(); NEXT; }
2114 
2115  case 0x44: { int c = ld_R_R<B,IYH,T::CC_DD>(); NEXT; }
2116  case 0x45: { int c = ld_R_R<B,IYL,T::CC_DD>(); NEXT; }
2117  case 0x4c: { int c = ld_R_R<C,IYH,T::CC_DD>(); NEXT; }
2118  case 0x4d: { int c = ld_R_R<C,IYL,T::CC_DD>(); NEXT; }
2119  case 0x54: { int c = ld_R_R<D,IYH,T::CC_DD>(); NEXT; }
2120  case 0x55: { int c = ld_R_R<D,IYL,T::CC_DD>(); NEXT; }
2121  case 0x5c: { int c = ld_R_R<E,IYH,T::CC_DD>(); NEXT; }
2122  case 0x5d: { int c = ld_R_R<E,IYL,T::CC_DD>(); NEXT; }
2123  case 0x7c: { int c = ld_R_R<A,IYH,T::CC_DD>(); NEXT; }
2124  case 0x7d: { int c = ld_R_R<A,IYL,T::CC_DD>(); NEXT; }
2125  case 0x60: { int c = ld_R_R<IYH,B,T::CC_DD>(); NEXT; }
2126  case 0x61: { int c = ld_R_R<IYH,C,T::CC_DD>(); NEXT; }
2127  case 0x62: { int c = ld_R_R<IYH,D,T::CC_DD>(); NEXT; }
2128  case 0x63: { int c = ld_R_R<IYH,E,T::CC_DD>(); NEXT; }
2129  case 0x65: { int c = ld_R_R<IYH,IYL,T::CC_DD>(); NEXT; }
2130  case 0x67: { int c = ld_R_R<IYH,A,T::CC_DD>(); NEXT; }
2131  case 0x68: { int c = ld_R_R<IYL,B,T::CC_DD>(); NEXT; }
2132  case 0x69: { int c = ld_R_R<IYL,C,T::CC_DD>(); NEXT; }
2133  case 0x6a: { int c = ld_R_R<IYL,D,T::CC_DD>(); NEXT; }
2134  case 0x6b: { int c = ld_R_R<IYL,E,T::CC_DD>(); NEXT; }
2135  case 0x6c: { int c = ld_R_R<IYL,IYH,T::CC_DD>(); NEXT; }
2136  case 0x6f: { int c = ld_R_R<IYL,A,T::CC_DD>(); NEXT; }
2137  case 0x70: { int c = ld_xix_R<IY,B>(); NEXT; }
2138  case 0x71: { int c = ld_xix_R<IY,C>(); NEXT; }
2139  case 0x72: { int c = ld_xix_R<IY,D>(); NEXT; }
2140  case 0x73: { int c = ld_xix_R<IY,E>(); NEXT; }
2141  case 0x74: { int c = ld_xix_R<IY,H>(); NEXT; }
2142  case 0x75: { int c = ld_xix_R<IY,L>(); NEXT; }
2143  case 0x77: { int c = ld_xix_R<IY,A>(); NEXT; }
2144  case 0x46: { int c = ld_R_xix<B,IY>(); NEXT; }
2145  case 0x4e: { int c = ld_R_xix<C,IY>(); NEXT; }
2146  case 0x56: { int c = ld_R_xix<D,IY>(); NEXT; }
2147  case 0x5e: { int c = ld_R_xix<E,IY>(); NEXT; }
2148  case 0x66: { int c = ld_R_xix<H,IY>(); NEXT; }
2149  case 0x6e: { int c = ld_R_xix<L,IY>(); NEXT; }
2150  case 0x7e: { int c = ld_R_xix<A,IY>(); NEXT; }
2151 
2152  case 0x84: { int c = add_a_R<IYH,T::CC_DD>(); NEXT; }
2153  case 0x85: { int c = add_a_R<IYL,T::CC_DD>(); NEXT; }
2154  case 0x86: { int c = add_a_xix<IY>(); NEXT; }
2155  case 0x8c: { int c = adc_a_R<IYH,T::CC_DD>(); NEXT; }
2156  case 0x8d: { int c = adc_a_R<IYL,T::CC_DD>(); NEXT; }
2157  case 0x8e: { int c = adc_a_xix<IY>(); NEXT; }
2158  case 0x94: { int c = sub_R<IYH,T::CC_DD>(); NEXT; }
2159  case 0x95: { int c = sub_R<IYL,T::CC_DD>(); NEXT; }
2160  case 0x96: { int c = sub_xix<IY>(); NEXT; }
2161  case 0x9c: { int c = sbc_a_R<IYH,T::CC_DD>(); NEXT; }
2162  case 0x9d: { int c = sbc_a_R<IYL,T::CC_DD>(); NEXT; }
2163  case 0x9e: { int c = sbc_a_xix<IY>(); NEXT; }
2164  case 0xa4: { int c = and_R<IYH,T::CC_DD>(); NEXT; }
2165  case 0xa5: { int c = and_R<IYL,T::CC_DD>(); NEXT; }
2166  case 0xa6: { int c = and_xix<IY>(); NEXT; }
2167  case 0xac: { int c = xor_R<IYH,T::CC_DD>(); NEXT; }
2168  case 0xad: { int c = xor_R<IYL,T::CC_DD>(); NEXT; }
2169  case 0xae: { int c = xor_xix<IY>(); NEXT; }
2170  case 0xb4: { int c = or_R<IYH,T::CC_DD>(); NEXT; }
2171  case 0xb5: { int c = or_R<IYL,T::CC_DD>(); NEXT; }
2172  case 0xb6: { int c = or_xix<IY>(); NEXT; }
2173  case 0xbc: { int c = cp_R<IYH,T::CC_DD>(); NEXT; }
2174  case 0xbd: { int c = cp_R<IYL,T::CC_DD>(); NEXT; }
2175  case 0xbe: { int c = cp_xix<IY>(); NEXT; }
2176 
2177  case 0xe1: { int c = pop_SS <IY,T::CC_DD>(); NEXT; }
2178  case 0xe5: { int c = push_SS<IY,T::CC_DD>(); NEXT; }
2179  case 0xe3: { int c = ex_xsp_SS<IY,T::CC_DD>(); NEXT; }
2180  case 0xe9: { int c = jp_SS<IY,T::CC_DD>(); NEXT; }
2181  case 0xf9: { int c = ld_sp_SS<IY,T::CC_DD>(); NEXT; }
2182  case 0xcb: ixy = getIY(); goto xx_cb;
2183  case 0xdd: T::add(T::CC_DD); goto opDD_2;
2184  case 0xfd: T::add(T::CC_DD); goto opFD_2;
2185  default: UNREACHABLE; return;
2186  }
2187 }
2188 #ifndef USE_COMPUTED_GOTO
2189  default: UNREACHABLE; return;
2190 }
2191 #endif
2192 
2193 xx_cb: {
2194  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_DD_CB);
2195  int8_t ofst = tmp & 0xFF;
2196  unsigned addr = (ixy + ofst) & 0xFFFF;
2197  byte xxcb_opcode = tmp >> 8;
2198  switch (xxcb_opcode) {
2199  case 0x00: { int c = rlc_xix_R<B>(addr); NEXT; }
2200  case 0x01: { int c = rlc_xix_R<C>(addr); NEXT; }
2201  case 0x02: { int c = rlc_xix_R<D>(addr); NEXT; }
2202  case 0x03: { int c = rlc_xix_R<E>(addr); NEXT; }
2203  case 0x04: { int c = rlc_xix_R<H>(addr); NEXT; }
2204  case 0x05: { int c = rlc_xix_R<L>(addr); NEXT; }
2205  case 0x06: { int c = rlc_xix_R<DUMMY>(addr); NEXT; }
2206  case 0x07: { int c = rlc_xix_R<A>(addr); NEXT; }
2207  case 0x08: { int c = rrc_xix_R<B>(addr); NEXT; }
2208  case 0x09: { int c = rrc_xix_R<C>(addr); NEXT; }
2209  case 0x0a: { int c = rrc_xix_R<D>(addr); NEXT; }
2210  case 0x0b: { int c = rrc_xix_R<E>(addr); NEXT; }
2211  case 0x0c: { int c = rrc_xix_R<H>(addr); NEXT; }
2212  case 0x0d: { int c = rrc_xix_R<L>(addr); NEXT; }
2213  case 0x0e: { int c = rrc_xix_R<DUMMY>(addr); NEXT; }
2214  case 0x0f: { int c = rrc_xix_R<A>(addr); NEXT; }
2215  case 0x10: { int c = rl_xix_R<B>(addr); NEXT; }
2216  case 0x11: { int c = rl_xix_R<C>(addr); NEXT; }
2217  case 0x12: { int c = rl_xix_R<D>(addr); NEXT; }
2218  case 0x13: { int c = rl_xix_R<E>(addr); NEXT; }
2219  case 0x14: { int c = rl_xix_R<H>(addr); NEXT; }
2220  case 0x15: { int c = rl_xix_R<L>(addr); NEXT; }
2221  case 0x16: { int c = rl_xix_R<DUMMY>(addr); NEXT; }
2222  case 0x17: { int c = rl_xix_R<A>(addr); NEXT; }
2223  case 0x18: { int c = rr_xix_R<B>(addr); NEXT; }
2224  case 0x19: { int c = rr_xix_R<C>(addr); NEXT; }
2225  case 0x1a: { int c = rr_xix_R<D>(addr); NEXT; }
2226  case 0x1b: { int c = rr_xix_R<E>(addr); NEXT; }
2227  case 0x1c: { int c = rr_xix_R<H>(addr); NEXT; }
2228  case 0x1d: { int c = rr_xix_R<L>(addr); NEXT; }
2229  case 0x1e: { int c = rr_xix_R<DUMMY>(addr); NEXT; }
2230  case 0x1f: { int c = rr_xix_R<A>(addr); NEXT; }
2231  case 0x20: { int c = sla_xix_R<B>(addr); NEXT; }
2232  case 0x21: { int c = sla_xix_R<C>(addr); NEXT; }
2233  case 0x22: { int c = sla_xix_R<D>(addr); NEXT; }
2234  case 0x23: { int c = sla_xix_R<E>(addr); NEXT; }
2235  case 0x24: { int c = sla_xix_R<H>(addr); NEXT; }
2236  case 0x25: { int c = sla_xix_R<L>(addr); NEXT; }
2237  case 0x26: { int c = sla_xix_R<DUMMY>(addr); NEXT; }
2238  case 0x27: { int c = sla_xix_R<A>(addr); NEXT; }
2239  case 0x28: { int c = sra_xix_R<B>(addr); NEXT; }
2240  case 0x29: { int c = sra_xix_R<C>(addr); NEXT; }
2241  case 0x2a: { int c = sra_xix_R<D>(addr); NEXT; }
2242  case 0x2b: { int c = sra_xix_R<E>(addr); NEXT; }
2243  case 0x2c: { int c = sra_xix_R<H>(addr); NEXT; }
2244  case 0x2d: { int c = sra_xix_R<L>(addr); NEXT; }
2245  case 0x2e: { int c = sra_xix_R<DUMMY>(addr); NEXT; }
2246  case 0x2f: { int c = sra_xix_R<A>(addr); NEXT; }
2247  case 0x30: { int c = T::isR800() ? sll2() : sll_xix_R<B>(addr); NEXT; }
2248  case 0x31: { int c = T::isR800() ? sll2() : sll_xix_R<C>(addr); NEXT; }
2249  case 0x32: { int c = T::isR800() ? sll2() : sll_xix_R<D>(addr); NEXT; }
2250  case 0x33: { int c = T::isR800() ? sll2() : sll_xix_R<E>(addr); NEXT; }
2251  case 0x34: { int c = T::isR800() ? sll2() : sll_xix_R<H>(addr); NEXT; }
2252  case 0x35: { int c = T::isR800() ? sll2() : sll_xix_R<L>(addr); NEXT; }
2253  case 0x36: { int c = T::isR800() ? sll2() : sll_xix_R<DUMMY>(addr); NEXT; }
2254  case 0x37: { int c = T::isR800() ? sll2() : sll_xix_R<A>(addr); NEXT; }
2255  case 0x38: { int c = srl_xix_R<B>(addr); NEXT; }
2256  case 0x39: { int c = srl_xix_R<C>(addr); NEXT; }
2257  case 0x3a: { int c = srl_xix_R<D>(addr); NEXT; }
2258  case 0x3b: { int c = srl_xix_R<E>(addr); NEXT; }
2259  case 0x3c: { int c = srl_xix_R<H>(addr); NEXT; }
2260  case 0x3d: { int c = srl_xix_R<L>(addr); NEXT; }
2261  case 0x3e: { int c = srl_xix_R<DUMMY>(addr); NEXT; }
2262  case 0x3f: { int c = srl_xix_R<A>(addr); NEXT; }
2263 
2264  case 0x40: case 0x41: case 0x42: case 0x43:
2265  case 0x44: case 0x45: case 0x46: case 0x47:
2266  { int c = bit_N_xix<0>(addr); NEXT; }
2267  case 0x48: case 0x49: case 0x4a: case 0x4b:
2268  case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2269  { int c = bit_N_xix<1>(addr); NEXT; }
2270  case 0x50: case 0x51: case 0x52: case 0x53:
2271  case 0x54: case 0x55: case 0x56: case 0x57:
2272  { int c = bit_N_xix<2>(addr); NEXT; }
2273  case 0x58: case 0x59: case 0x5a: case 0x5b:
2274  case 0x5c: case 0x5d: case 0x5e: case 0x5f:
2275  { int c = bit_N_xix<3>(addr); NEXT; }
2276  case 0x60: case 0x61: case 0x62: case 0x63:
2277  case 0x64: case 0x65: case 0x66: case 0x67:
2278  { int c = bit_N_xix<4>(addr); NEXT; }
2279  case 0x68: case 0x69: case 0x6a: case 0x6b:
2280  case 0x6c: case 0x6d: case 0x6e: case 0x6f:
2281  { int c = bit_N_xix<5>(addr); NEXT; }
2282  case 0x70: case 0x71: case 0x72: case 0x73:
2283  case 0x74: case 0x75: case 0x76: case 0x77:
2284  { int c = bit_N_xix<6>(addr); NEXT; }
2285  case 0x78: case 0x79: case 0x7a: case 0x7b:
2286  case 0x7c: case 0x7d: case 0x7e: case 0x7f:
2287  { int c = bit_N_xix<7>(addr); NEXT; }
2288 
2289  case 0x80: { int c = res_N_xix_R<0,B>(addr); NEXT; }
2290  case 0x81: { int c = res_N_xix_R<0,C>(addr); NEXT; }
2291  case 0x82: { int c = res_N_xix_R<0,D>(addr); NEXT; }
2292  case 0x83: { int c = res_N_xix_R<0,E>(addr); NEXT; }
2293  case 0x84: { int c = res_N_xix_R<0,H>(addr); NEXT; }
2294  case 0x85: { int c = res_N_xix_R<0,L>(addr); NEXT; }
2295  case 0x87: { int c = res_N_xix_R<0,A>(addr); NEXT; }
2296  case 0x88: { int c = res_N_xix_R<1,B>(addr); NEXT; }
2297  case 0x89: { int c = res_N_xix_R<1,C>(addr); NEXT; }
2298  case 0x8a: { int c = res_N_xix_R<1,D>(addr); NEXT; }
2299  case 0x8b: { int c = res_N_xix_R<1,E>(addr); NEXT; }
2300  case 0x8c: { int c = res_N_xix_R<1,H>(addr); NEXT; }
2301  case 0x8d: { int c = res_N_xix_R<1,L>(addr); NEXT; }
2302  case 0x8f: { int c = res_N_xix_R<1,A>(addr); NEXT; }
2303  case 0x90: { int c = res_N_xix_R<2,B>(addr); NEXT; }
2304  case 0x91: { int c = res_N_xix_R<2,C>(addr); NEXT; }
2305  case 0x92: { int c = res_N_xix_R<2,D>(addr); NEXT; }
2306  case 0x93: { int c = res_N_xix_R<2,E>(addr); NEXT; }
2307  case 0x94: { int c = res_N_xix_R<2,H>(addr); NEXT; }
2308  case 0x95: { int c = res_N_xix_R<2,L>(addr); NEXT; }
2309  case 0x97: { int c = res_N_xix_R<2,A>(addr); NEXT; }
2310  case 0x98: { int c = res_N_xix_R<3,B>(addr); NEXT; }
2311  case 0x99: { int c = res_N_xix_R<3,C>(addr); NEXT; }
2312  case 0x9a: { int c = res_N_xix_R<3,D>(addr); NEXT; }
2313  case 0x9b: { int c = res_N_xix_R<3,E>(addr); NEXT; }
2314  case 0x9c: { int c = res_N_xix_R<3,H>(addr); NEXT; }
2315  case 0x9d: { int c = res_N_xix_R<3,L>(addr); NEXT; }
2316  case 0x9f: { int c = res_N_xix_R<3,A>(addr); NEXT; }
2317  case 0xa0: { int c = res_N_xix_R<4,B>(addr); NEXT; }
2318  case 0xa1: { int c = res_N_xix_R<4,C>(addr); NEXT; }
2319  case 0xa2: { int c = res_N_xix_R<4,D>(addr); NEXT; }
2320  case 0xa3: { int c = res_N_xix_R<4,E>(addr); NEXT; }
2321  case 0xa4: { int c = res_N_xix_R<4,H>(addr); NEXT; }
2322  case 0xa5: { int c = res_N_xix_R<4,L>(addr); NEXT; }
2323  case 0xa7: { int c = res_N_xix_R<4,A>(addr); NEXT; }
2324  case 0xa8: { int c = res_N_xix_R<5,B>(addr); NEXT; }
2325  case 0xa9: { int c = res_N_xix_R<5,C>(addr); NEXT; }
2326  case 0xaa: { int c = res_N_xix_R<5,D>(addr); NEXT; }
2327  case 0xab: { int c = res_N_xix_R<5,E>(addr); NEXT; }
2328  case 0xac: { int c = res_N_xix_R<5,H>(addr); NEXT; }
2329  case 0xad: { int c = res_N_xix_R<5,L>(addr); NEXT; }
2330  case 0xaf: { int c = res_N_xix_R<5,A>(addr); NEXT; }
2331  case 0xb0: { int c = res_N_xix_R<6,B>(addr); NEXT; }
2332  case 0xb1: { int c = res_N_xix_R<6,C>(addr); NEXT; }
2333  case 0xb2: { int c = res_N_xix_R<6,D>(addr); NEXT; }
2334  case 0xb3: { int c = res_N_xix_R<6,E>(addr); NEXT; }
2335  case 0xb4: { int c = res_N_xix_R<6,H>(addr); NEXT; }
2336  case 0xb5: { int c = res_N_xix_R<6,L>(addr); NEXT; }
2337  case 0xb7: { int c = res_N_xix_R<6,A>(addr); NEXT; }
2338  case 0xb8: { int c = res_N_xix_R<7,B>(addr); NEXT; }
2339  case 0xb9: { int c = res_N_xix_R<7,C>(addr); NEXT; }
2340  case 0xba: { int c = res_N_xix_R<7,D>(addr); NEXT; }
2341  case 0xbb: { int c = res_N_xix_R<7,E>(addr); NEXT; }
2342  case 0xbc: { int c = res_N_xix_R<7,H>(addr); NEXT; }
2343  case 0xbd: { int c = res_N_xix_R<7,L>(addr); NEXT; }
2344  case 0xbf: { int c = res_N_xix_R<7,A>(addr); NEXT; }
2345  case 0x86: { int c = res_N_xix_R<0,DUMMY>(addr); NEXT; }
2346  case 0x8e: { int c = res_N_xix_R<1,DUMMY>(addr); NEXT; }
2347  case 0x96: { int c = res_N_xix_R<2,DUMMY>(addr); NEXT; }
2348  case 0x9e: { int c = res_N_xix_R<3,DUMMY>(addr); NEXT; }
2349  case 0xa6: { int c = res_N_xix_R<4,DUMMY>(addr); NEXT; }
2350  case 0xae: { int c = res_N_xix_R<5,DUMMY>(addr); NEXT; }
2351  case 0xb6: { int c = res_N_xix_R<6,DUMMY>(addr); NEXT; }
2352  case 0xbe: { int c = res_N_xix_R<7,DUMMY>(addr); NEXT; }
2353 
2354  case 0xc0: { int c = set_N_xix_R<0,B>(addr); NEXT; }
2355  case 0xc1: { int c = set_N_xix_R<0,C>(addr); NEXT; }
2356  case 0xc2: { int c = set_N_xix_R<0,D>(addr); NEXT; }
2357  case 0xc3: { int c = set_N_xix_R<0,E>(addr); NEXT; }
2358  case 0xc4: { int c = set_N_xix_R<0,H>(addr); NEXT; }
2359  case 0xc5: { int c = set_N_xix_R<0,L>(addr); NEXT; }
2360  case 0xc7: { int c = set_N_xix_R<0,A>(addr); NEXT; }
2361  case 0xc8: { int c = set_N_xix_R<1,B>(addr); NEXT; }
2362  case 0xc9: { int c = set_N_xix_R<1,C>(addr); NEXT; }
2363  case 0xca: { int c = set_N_xix_R<1,D>(addr); NEXT; }
2364  case 0xcb: { int c = set_N_xix_R<1,E>(addr); NEXT; }
2365  case 0xcc: { int c = set_N_xix_R<1,H>(addr); NEXT; }
2366  case 0xcd: { int c = set_N_xix_R<1,L>(addr); NEXT; }
2367  case 0xcf: { int c = set_N_xix_R<1,A>(addr); NEXT; }
2368  case 0xd0: { int c = set_N_xix_R<2,B>(addr); NEXT; }
2369  case 0xd1: { int c = set_N_xix_R<2,C>(addr); NEXT; }
2370  case 0xd2: { int c = set_N_xix_R<2,D>(addr); NEXT; }
2371  case 0xd3: { int c = set_N_xix_R<2,E>(addr); NEXT; }
2372  case 0xd4: { int c = set_N_xix_R<2,H>(addr); NEXT; }
2373  case 0xd5: { int c = set_N_xix_R<2,L>(addr); NEXT; }
2374  case 0xd7: { int c = set_N_xix_R<2,A>(addr); NEXT; }
2375  case 0xd8: { int c = set_N_xix_R<3,B>(addr); NEXT; }
2376  case 0xd9: { int c = set_N_xix_R<3,C>(addr); NEXT; }
2377  case 0xda: { int c = set_N_xix_R<3,D>(addr); NEXT; }
2378  case 0xdb: { int c = set_N_xix_R<3,E>(addr); NEXT; }
2379  case 0xdc: { int c = set_N_xix_R<3,H>(addr); NEXT; }
2380  case 0xdd: { int c = set_N_xix_R<3,L>(addr); NEXT; }
2381  case 0xdf: { int c = set_N_xix_R<3,A>(addr); NEXT; }
2382  case 0xe0: { int c = set_N_xix_R<4,B>(addr); NEXT; }
2383  case 0xe1: { int c = set_N_xix_R<4,C>(addr); NEXT; }
2384  case 0xe2: { int c = set_N_xix_R<4,D>(addr); NEXT; }
2385  case 0xe3: { int c = set_N_xix_R<4,E>(addr); NEXT; }
2386  case 0xe4: { int c = set_N_xix_R<4,H>(addr); NEXT; }
2387  case 0xe5: { int c = set_N_xix_R<4,L>(addr); NEXT; }
2388  case 0xe7: { int c = set_N_xix_R<4,A>(addr); NEXT; }
2389  case 0xe8: { int c = set_N_xix_R<5,B>(addr); NEXT; }
2390  case 0xe9: { int c = set_N_xix_R<5,C>(addr); NEXT; }
2391  case 0xea: { int c = set_N_xix_R<5,D>(addr); NEXT; }
2392  case 0xeb: { int c = set_N_xix_R<5,E>(addr); NEXT; }
2393  case 0xec: { int c = set_N_xix_R<5,H>(addr); NEXT; }
2394  case 0xed: { int c = set_N_xix_R<5,L>(addr); NEXT; }
2395  case 0xef: { int c = set_N_xix_R<5,A>(addr); NEXT; }
2396  case 0xf0: { int c = set_N_xix_R<6,B>(addr); NEXT; }
2397  case 0xf1: { int c = set_N_xix_R<6,C>(addr); NEXT; }
2398  case 0xf2: { int c = set_N_xix_R<6,D>(addr); NEXT; }
2399  case 0xf3: { int c = set_N_xix_R<6,E>(addr); NEXT; }
2400  case 0xf4: { int c = set_N_xix_R<6,H>(addr); NEXT; }
2401  case 0xf5: { int c = set_N_xix_R<6,L>(addr); NEXT; }
2402  case 0xf7: { int c = set_N_xix_R<6,A>(addr); NEXT; }
2403  case 0xf8: { int c = set_N_xix_R<7,B>(addr); NEXT; }
2404  case 0xf9: { int c = set_N_xix_R<7,C>(addr); NEXT; }
2405  case 0xfa: { int c = set_N_xix_R<7,D>(addr); NEXT; }
2406  case 0xfb: { int c = set_N_xix_R<7,E>(addr); NEXT; }
2407  case 0xfc: { int c = set_N_xix_R<7,H>(addr); NEXT; }
2408  case 0xfd: { int c = set_N_xix_R<7,L>(addr); NEXT; }
2409  case 0xff: { int c = set_N_xix_R<7,A>(addr); NEXT; }
2410  case 0xc6: { int c = set_N_xix_R<0,DUMMY>(addr); NEXT; }
2411  case 0xce: { int c = set_N_xix_R<1,DUMMY>(addr); NEXT; }
2412  case 0xd6: { int c = set_N_xix_R<2,DUMMY>(addr); NEXT; }
2413  case 0xde: { int c = set_N_xix_R<3,DUMMY>(addr); NEXT; }
2414  case 0xe6: { int c = set_N_xix_R<4,DUMMY>(addr); NEXT; }
2415  case 0xee: { int c = set_N_xix_R<5,DUMMY>(addr); NEXT; }
2416  case 0xf6: { int c = set_N_xix_R<6,DUMMY>(addr); NEXT; }
2417  case 0xfe: { int c = set_N_xix_R<7,DUMMY>(addr); NEXT; }
2418  default: UNREACHABLE;
2419  }
2420  }
2421 }
2422 
2423 template<class T> inline void CPUCore<T>::cpuTracePre()
2424 {
2425  start_pc = getPC();
2426 }
2427 template<class T> inline void CPUCore<T>::cpuTracePost()
2428 {
2429  if (unlikely(tracingEnabled)) {
2430  cpuTracePost_slow();
2431  }
2432 }
2433 template<class T> void CPUCore<T>::cpuTracePost_slow()
2434 {
2435  byte opbuf[4];
2436  string dasmOutput;
2437  dasm(*interface, start_pc, opbuf, dasmOutput, T::getTimeFast());
2438  std::cout << std::setfill('0') << std::hex << std::setw(4) << start_pc
2439  << " : " << dasmOutput
2440  << " AF=" << std::setw(4) << getAF()
2441  << " BC=" << std::setw(4) << getBC()
2442  << " DE=" << std::setw(4) << getDE()
2443  << " HL=" << std::setw(4) << getHL()
2444  << " IX=" << std::setw(4) << getIX()
2445  << " IY=" << std::setw(4) << getIY()
2446  << " SP=" << std::setw(4) << getSP()
2447  << std::endl << std::dec;
2448 }
2449 
2450 template<class T> void CPUCore<T>::executeSlow()
2451 {
2452  if (unlikely(false && nmiEdge)) {
2453  // Note: NMIs are disabled, see also raiseNMI()
2454  nmiEdge = false;
2455  nmi(); // NMI occured
2456  } else if (unlikely(IRQStatus && getIFF1() && !getAfterEI())) {
2457  // normal interrupt
2458  if (unlikely(getAfterLDAI())) {
2459  // HACK!!!
2460  // The 'ld a,i' or 'ld a,r' instruction copies the IFF2
2461  // bit to the V flag. Though when the Z80 accepts an
2462  // IRQ directly after this instruction, the V flag is 0
2463  // (instead of the expected value 1). This can probably
2464  // be explained if you look at the pipeline of the Z80.
2465  // But for speed reasons we implement it here as a
2466  // fix-up (a hack) in the IRQ routine. This behaviour
2467  // is actually a bug in the Z80.
2468  // Thanks to n_n for reporting this behaviour. I think
2469  // this was discovered by GuyveR800. Also thanks to
2470  // n_n for writing a test program that demonstrates
2471  // this quirk.
2472  // I also wrote a test program that demonstrates this
2473  // behaviour is the same whether 'ld a,i' is preceded
2474  // by a 'ei' instruction or not (so it's not caused by
2475  // the 'delayed IRQ acceptance of ei').
2476  assert(getF() & V_FLAG);
2477  setF(getF() & ~V_FLAG);
2478  }
2479  IRQAccept.signal();
2480  switch (getIM()) {
2481  case 0: irq0();
2482  break;
2483  case 1: irq1();
2484  break;
2485  case 2: irq2();
2486  break;
2487  default:
2488  UNREACHABLE;
2489  }
2490  } else if (unlikely(getHALT())) {
2491  // in halt mode
2492  incR(T::advanceHalt(T::haltStates(), scheduler.getNext()));
2493  setSlowInstructions();
2494  } else {
2495  assert(isSameAfter());
2496  clearNextAfter();
2497  cpuTracePre();
2498  assert(T::limitReached()); // we want only one instruction
2499  executeInstructions();
2500  cpuTracePost();
2501  copyNextAfter();
2502  }
2503 }
2504 
2505 template<class T> void CPUCore<T>::execute(bool fastForward)
2506 {
2507  // In fast-forward mode, breakpoints, watchpoints or debug condtions
2508  // won't trigger. It is possible we already are in break mode, but
2509  // break is ignored in fast-forward mode.
2510  assert(fastForward || !interface->isBreaked());
2511  if (fastForward) {
2512  interface->setFastForward(true);
2513  }
2514  execute2(fastForward);
2515  interface->setFastForward(false);
2516 }
2517 
2518 template<class T> void CPUCore<T>::execute2(bool fastForward)
2519 {
2520  // note: Don't use getTimeFast() here, because 'once in a while' we
2521  // need to CPUClock::sync() to avoid overflow.
2522  // Should be done at least once per second (approx). So only
2523  // once in this method is enough.
2524  scheduler.schedule(T::getTime());
2525  setSlowInstructions();
2526 
2527  if (!fastForward && (interface->isContinue() || interface->isStep())) {
2528  // at least one instruction
2529  interface->setContinue(false);
2530  executeSlow();
2531  scheduler.schedule(T::getTimeFast());
2532  --slowInstructions;
2533  if (interface->isStep()) {
2534  interface->setStep(false);
2535  interface->doBreak();
2536  return;
2537  }
2538  }
2539 
2540  // Note: we call scheduler _after_ executing the instruction and before
2541  // deciding between executeFast() and executeSlow() (because a
2542  // SyncPoint could set an IRQ and then we must choose executeSlow())
2543  if (fastForward ||
2544  (!interface->anyBreakPoints() && !tracingEnabled)) {
2545  // fast path, no breakpoints, no tracing
2546  while (!needExitCPULoop()) {
2547  if (slowInstructions) {
2548  --slowInstructions;
2549  executeSlow();
2550  scheduler.schedule(T::getTimeFast());
2551  } else {
2552  while (slowInstructions == 0) {
2553  T::enableLimit(); // does CPUClock::sync()
2554  if (likely(!T::limitReached())) {
2555  // multiple instructions
2556  assert(isSameAfter());
2557  executeInstructions();
2558  assert(isSameAfter());
2559  }
2560  scheduler.schedule(T::getTimeFast());
2561  if (needExitCPULoop()) return;
2562  }
2563  }
2564  }
2565  } else {
2566  while (!needExitCPULoop()) {
2567  if (interface->checkBreakPoints(getPC())) {
2568  assert(interface->isBreaked());
2569  break;
2570  }
2571  if (slowInstructions == 0) {
2572  cpuTracePre();
2573  assert(T::limitReached()); // only one instruction
2574  assert(isSameAfter());
2575  executeInstructions();
2576  assert(isSameAfter());
2577  cpuTracePost();
2578  } else {
2579  --slowInstructions;
2580  executeSlow();
2581  }
2582  // Don't use getTimeFast() here, we need a call to
2583  // CPUClock::sync() 'once in a while'. (During a
2584  // reverse fast-forward this wasn't always the case).
2585  scheduler.schedule(T::getTime());
2586  }
2587  }
2588 }
2589 
2590 template<class T> template<Reg8 R8> ALWAYS_INLINE byte CPUCore<T>::get8() const {
2591  if (R8 == A) { return getA(); }
2592  else if (R8 == F) { return getF(); }
2593  else if (R8 == B) { return getB(); }
2594  else if (R8 == C) { return getC(); }
2595  else if (R8 == D) { return getD(); }
2596  else if (R8 == E) { return getE(); }
2597  else if (R8 == H) { return getH(); }
2598  else if (R8 == L) { return getL(); }
2599  else if (R8 == IXH) { return getIXh(); }
2600  else if (R8 == IXL) { return getIXl(); }
2601  else if (R8 == IYH) { return getIYh(); }
2602  else if (R8 == IYL) { return getIYl(); }
2603  else if (R8 == REG_I) { return getI(); }
2604  else if (R8 == REG_R) { return getR(); }
2605  else if (R8 == DUMMY) { return 0; }
2606  else { UNREACHABLE; return 0; }
2607 }
2608 template<class T> template<Reg16 R16> ALWAYS_INLINE unsigned CPUCore<T>::get16() const {
2609  if (R16 == AF) { return getAF(); }
2610  else if (R16 == BC) { return getBC(); }
2611  else if (R16 == DE) { return getDE(); }
2612  else if (R16 == HL) { return getHL(); }
2613  else if (R16 == IX) { return getIX(); }
2614  else if (R16 == IY) { return getIY(); }
2615  else if (R16 == SP) { return getSP(); }
2616  else { UNREACHABLE; return 0; }
2617 }
2618 template<class T> template<Reg8 R8> ALWAYS_INLINE void CPUCore<T>::set8(byte x) {
2619  if (R8 == A) { setA(x); }
2620  else if (R8 == F) { setF(x); }
2621  else if (R8 == B) { setB(x); }
2622  else if (R8 == C) { setC(x); }
2623  else if (R8 == D) { setD(x); }
2624  else if (R8 == E) { setE(x); }
2625  else if (R8 == H) { setH(x); }
2626  else if (R8 == L) { setL(x); }
2627  else if (R8 == IXH) { setIXh(x); }
2628  else if (R8 == IXL) { setIXl(x); }
2629  else if (R8 == IYH) { setIYh(x); }
2630  else if (R8 == IYL) { setIYl(x); }
2631  else if (R8 == REG_I) { setI(x); }
2632  else if (R8 == REG_R) { setR(x); }
2633  else if (R8 == DUMMY) { /* nothing */ }
2634  else { UNREACHABLE; }
2635 }
2636 template<class T> template<Reg16 R16> ALWAYS_INLINE void CPUCore<T>::set16(unsigned x) {
2637  if (R16 == AF) { setAF(x); }
2638  else if (R16 == BC) { setBC(x); }
2639  else if (R16 == DE) { setDE(x); }
2640  else if (R16 == HL) { setHL(x); }
2641  else if (R16 == IX) { setIX(x); }
2642  else if (R16 == IY) { setIY(x); }
2643  else if (R16 == SP) { setSP(x); }
2644  else { UNREACHABLE; }
2645 }
2646 
2647 // LD r,r
2648 template<class T> template<Reg8 DST, Reg8 SRC, int EE> int CPUCore<T>::ld_R_R() {
2649  set8<DST>(get8<SRC>()); return T::CC_LD_R_R + EE;
2650 }
2651 
2652 // LD SP,ss
2653 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_sp_SS() {
2654  setSP(get16<REG>()); return T::CC_LD_SP_HL + EE;
2655 }
2656 
2657 // LD (ss),a
2658 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_a() {
2659  T::setMemPtr((getA() << 8) | ((get16<REG>() + 1) & 0xFF));
2660  WRMEM(get16<REG>(), getA(), T::CC_LD_SS_A_1);
2661  return T::CC_LD_SS_A;
2662 }
2663 
2664 // LD (HL),r
2665 template<class T> template<Reg8 SRC> int CPUCore<T>::ld_xhl_R() {
2666  WRMEM(getHL(), get8<SRC>(), T::CC_LD_HL_R_1);
2667  return T::CC_LD_HL_R;
2668 }
2669 
2670 // LD (IXY+e),r
2671 template<class T> template<Reg16 IXY, Reg8 SRC> int CPUCore<T>::ld_xix_R() {
2672  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_XIX_R_1);
2673  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2674  T::setMemPtr(addr);
2675  WRMEM(addr, get8<SRC>(), T::CC_DD + T::CC_LD_XIX_R_2);
2676  return T::CC_DD + T::CC_LD_XIX_R;
2677 }
2678 
2679 // LD (HL),n
2680 template<class T> int CPUCore<T>::ld_xhl_byte() {
2681  byte val = RDMEM_OPCODE(T::CC_LD_HL_N_1);
2682  WRMEM(getHL(), val, T::CC_LD_HL_N_2);
2683  return T::CC_LD_HL_N;
2684 }
2685 
2686 // LD (IXY+e),n
2687 template<class T> template<Reg16 IXY> int CPUCore<T>::ld_xix_byte() {
2688  unsigned tmp = RD_WORD_PC(T::CC_DD + T::CC_LD_XIX_N_1);
2689  int8_t ofst = tmp & 0xFF;
2690  byte val = tmp >> 8;
2691  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2692  T::setMemPtr(addr);
2693  WRMEM(addr, val, T::CC_DD + T::CC_LD_XIX_N_2);
2694  return T::CC_DD + T::CC_LD_XIX_N;
2695 }
2696 
2697 // LD (nn),A
2698 template<class T> int CPUCore<T>::ld_xbyte_a() {
2699  unsigned x = RD_WORD_PC(T::CC_LD_NN_A_1);
2700  T::setMemPtr((getA() << 8) | ((x + 1) & 0xFF));
2701  WRMEM(x, getA(), T::CC_LD_NN_A_2);
2702  return T::CC_LD_NN_A;
2703 }
2704 
2705 // LD (nn),ss
2706 template<class T> template<int EE> inline int CPUCore<T>::WR_NN_Y(unsigned reg) {
2707  unsigned addr = RD_WORD_PC(T::CC_LD_XX_HL_1 + EE);
2708  T::setMemPtr(addr + 1);
2709  WR_WORD(addr, reg, T::CC_LD_XX_HL_2 + EE);
2710  return T::CC_LD_XX_HL + EE;
2711 }
2712 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_xword_SS() {
2713  return WR_NN_Y<EE >(get16<REG>());
2714 }
2715 template<class T> template<Reg16 REG> int CPUCore<T>::ld_xword_SS_ED() {
2716  return WR_NN_Y<T::EE_ED>(get16<REG>());
2717 }
2718 
2719 // LD A,(ss)
2720 template<class T> template<Reg16 REG> int CPUCore<T>::ld_a_SS() {
2721  T::setMemPtr(get16<REG>() + 1);
2722  setA(RDMEM(get16<REG>(), T::CC_LD_A_SS_1));
2723  return T::CC_LD_A_SS;
2724 }
2725 
2726 // LD A,(nn)
2727 template<class T> int CPUCore<T>::ld_a_xbyte() {
2728  unsigned addr = RD_WORD_PC(T::CC_LD_A_NN_1);
2729  T::setMemPtr(addr + 1);
2730  setA(RDMEM(addr, T::CC_LD_A_NN_2));
2731  return T::CC_LD_A_NN;
2732 }
2733 
2734 // LD r,n
2735 template<class T> template<Reg8 DST, int EE> int CPUCore<T>::ld_R_byte() {
2736  set8<DST>(RDMEM_OPCODE(T::CC_LD_R_N_1 + EE)); return T::CC_LD_R_N + EE;
2737 }
2738 
2739 // LD r,(hl)
2740 template<class T> template<Reg8 DST> int CPUCore<T>::ld_R_xhl() {
2741  set8<DST>(RDMEM(getHL(), T::CC_LD_R_HL_1)); return T::CC_LD_R_HL;
2742 }
2743 
2744 // LD r,(IXY+e)
2745 template<class T> template<Reg8 DST, Reg16 IXY> int CPUCore<T>::ld_R_xix() {
2746  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_LD_R_XIX_1);
2747  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2748  T::setMemPtr(addr);
2749  set8<DST>(RDMEM(addr, T::CC_DD + T::CC_LD_R_XIX_2));
2750  return T::CC_DD + T::CC_LD_R_XIX;
2751 }
2752 
2753 // LD ss,(nn)
2754 template<class T> template<int EE> inline unsigned CPUCore<T>::RD_P_XX() {
2755  unsigned addr = RD_WORD_PC(T::CC_LD_HL_XX_1 + EE);
2756  T::setMemPtr(addr + 1);
2757  unsigned result = RD_WORD(addr, T::CC_LD_HL_XX_2 + EE);
2758  return result;
2759 }
2760 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_xword() {
2761  set16<REG>(RD_P_XX<EE>()); return T::CC_LD_HL_XX + EE;
2762 }
2763 template<class T> template<Reg16 REG> int CPUCore<T>::ld_SS_xword_ED() {
2764  set16<REG>(RD_P_XX<T::EE_ED>()); return T::CC_LD_HL_XX + T::EE_ED;
2765 }
2766 
2767 // LD ss,nn
2768 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ld_SS_word() {
2769  set16<REG>(RD_WORD_PC(T::CC_LD_SS_NN_1 + EE)); return T::CC_LD_SS_NN + EE;
2770 }
2771 
2772 
2773 // ADC A,r
2774 template<class T> inline void CPUCore<T>::ADC(byte reg) {
2775  unsigned res = getA() + reg + ((getF() & C_FLAG) ? 1 : 0);
2776  byte f = ((res & 0x100) ? C_FLAG : 0) |
2777  ((getA() ^ res ^ reg) & H_FLAG) |
2778  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2779  0; // N_FLAG
2780  if (T::isR800()) {
2781  f |= ZSTable[res & 0xFF];
2782  f |= getF() & (X_FLAG | Y_FLAG);
2783  } else {
2784  f |= ZSXYTable[res & 0xFF];
2785  }
2786  setF(f);
2787  setA(res);
2788 }
2789 template<class T> inline int CPUCore<T>::adc_a_a() {
2790  unsigned res = 2 * getA() + ((getF() & C_FLAG) ? 1 : 0);
2791  byte f = ((res & 0x100) ? C_FLAG : 0) |
2792  (res & H_FLAG) |
2793  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2794  0; // N_FLAG
2795  if (T::isR800()) {
2796  f |= ZSTable[res & 0xFF];
2797  f |= getF() & (X_FLAG | Y_FLAG);
2798  } else {
2799  f |= ZSXYTable[res & 0xFF];
2800  }
2801  setF(f);
2802  setA(res);
2803  return T::CC_CP_R;
2804 }
2805 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::adc_a_R() {
2806  ADC(get8<SRC>()); return T::CC_CP_R + EE;
2807 }
2808 template<class T> int CPUCore<T>::adc_a_byte() {
2809  ADC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2810 }
2811 template<class T> int CPUCore<T>::adc_a_xhl() {
2812  ADC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2813 }
2814 template<class T> template<Reg16 IXY> int CPUCore<T>::adc_a_xix() {
2815  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2816  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2817  T::setMemPtr(addr);
2818  ADC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2819  return T::CC_DD + T::CC_CP_XIX;
2820 }
2821 
2822 // ADD A,r
2823 template<class T> inline void CPUCore<T>::ADD(byte reg) {
2824  unsigned res = getA() + reg;
2825  byte f = ((res & 0x100) ? C_FLAG : 0) |
2826  ((getA() ^ res ^ reg) & H_FLAG) |
2827  (((getA() ^ res) & (reg ^ res) & 0x80) >> 5) | // V_FLAG
2828  0; // N_FLAG
2829  if (T::isR800()) {
2830  f |= ZSTable[res & 0xFF];
2831  f |= getF() & (X_FLAG | Y_FLAG);
2832  } else {
2833  f |= ZSXYTable[res & 0xFF];
2834  }
2835  setF(f);
2836  setA(res);
2837 }
2838 template<class T> inline int CPUCore<T>::add_a_a() {
2839  unsigned res = 2 * getA();
2840  byte f = ((res & 0x100) ? C_FLAG : 0) |
2841  (res & H_FLAG) |
2842  (((getA() ^ res) & 0x80) >> 5) | // V_FLAG
2843  0; // N_FLAG
2844  if (T::isR800()) {
2845  f |= ZSTable[res & 0xFF];
2846  f |= getF() & (X_FLAG | Y_FLAG);
2847  } else {
2848  f |= ZSXYTable[res & 0xFF];
2849  }
2850  setF(f);
2851  setA(res);
2852  return T::CC_CP_R;
2853 }
2854 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::add_a_R() {
2855  ADD(get8<SRC>()); return T::CC_CP_R + EE;
2856 }
2857 template<class T> int CPUCore<T>::add_a_byte() {
2858  ADD(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2859 }
2860 template<class T> int CPUCore<T>::add_a_xhl() {
2861  ADD(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2862 }
2863 template<class T> template<Reg16 IXY> int CPUCore<T>::add_a_xix() {
2864  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2865  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2866  T::setMemPtr(addr);
2867  ADD(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2868  return T::CC_DD + T::CC_CP_XIX;
2869 }
2870 
2871 // AND r
2872 template<class T> inline void CPUCore<T>::AND(byte reg) {
2873  setA(getA() & reg);
2874  byte f = 0;
2875  if (T::isR800()) {
2876  f |= ZSPHTable[getA()];
2877  f |= getF() & (X_FLAG | Y_FLAG);
2878  } else {
2879  f |= ZSPXYTable[getA()] | H_FLAG;
2880  }
2881  setF(f);
2882 }
2883 template<class T> int CPUCore<T>::and_a() {
2884  byte f = 0;
2885  if (T::isR800()) {
2886  f |= ZSPHTable[getA()];
2887  f |= getF() & (X_FLAG | Y_FLAG);
2888  } else {
2889  f |= ZSPXYTable[getA()] | H_FLAG;
2890  }
2891  setF(f);
2892  return T::CC_CP_R;
2893 }
2894 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::and_R() {
2895  AND(get8<SRC>()); return T::CC_CP_R + EE;
2896 }
2897 template<class T> int CPUCore<T>::and_byte() {
2898  AND(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2899 }
2900 template<class T> int CPUCore<T>::and_xhl() {
2901  AND(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2902 }
2903 template<class T> template<Reg16 IXY> int CPUCore<T>::and_xix() {
2904  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2905  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2906  T::setMemPtr(addr);
2907  AND(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2908  return T::CC_DD + T::CC_CP_XIX;
2909 }
2910 
2911 // CP r
2912 template<class T> inline void CPUCore<T>::CP(byte reg) {
2913  unsigned q = getA() - reg;
2914  byte f = ZSTable[q & 0xFF] |
2915  ((q & 0x100) ? C_FLAG : 0) |
2916  N_FLAG |
2917  ((getA() ^ q ^ reg) & H_FLAG) |
2918  (((reg ^ getA()) & (getA() ^ q) & 0x80) >> 5); // V_FLAG
2919  if (T::isR800()) {
2920  f |= getF() & (X_FLAG | Y_FLAG);
2921  } else {
2922  f |= reg & (X_FLAG | Y_FLAG); // XY from operand, not from result
2923  }
2924  setF(f);
2925 }
2926 template<class T> int CPUCore<T>::cp_a() {
2927  byte f = ZS0 | N_FLAG;
2928  if (T::isR800()) {
2929  f |= getF() & (X_FLAG | Y_FLAG);
2930  } else {
2931  f |= getA() & (X_FLAG | Y_FLAG); // XY from operand, not from result
2932  }
2933  setF(f);
2934  return T::CC_CP_R;
2935 }
2936 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::cp_R() {
2937  CP(get8<SRC>()); return T::CC_CP_R + EE;
2938 }
2939 template<class T> int CPUCore<T>::cp_byte() {
2940  CP(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2941 }
2942 template<class T> int CPUCore<T>::cp_xhl() {
2943  CP(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2944 }
2945 template<class T> template<Reg16 IXY> int CPUCore<T>::cp_xix() {
2946  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2947  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2948  T::setMemPtr(addr);
2949  CP(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2950  return T::CC_DD + T::CC_CP_XIX;
2951 }
2952 
2953 // OR r
2954 template<class T> inline void CPUCore<T>::OR(byte reg) {
2955  setA(getA() | reg);
2956  byte f = 0;
2957  if (T::isR800()) {
2958  f |= ZSPTable[getA()];
2959  f |= getF() & (X_FLAG | Y_FLAG);
2960  } else {
2961  f |= ZSPXYTable[getA()];
2962  }
2963  setF(f);
2964 }
2965 template<class T> int CPUCore<T>::or_a() {
2966  byte f = 0;
2967  if (T::isR800()) {
2968  f |= ZSPTable[getA()];
2969  f |= getF() & (X_FLAG | Y_FLAG);
2970  } else {
2971  f |= ZSPXYTable[getA()];
2972  }
2973  setF(f);
2974  return T::CC_CP_R;
2975 }
2976 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::or_R() {
2977  OR(get8<SRC>()); return T::CC_CP_R + EE;
2978 }
2979 template<class T> int CPUCore<T>::or_byte() {
2980  OR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
2981 }
2982 template<class T> int CPUCore<T>::or_xhl() {
2983  OR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
2984 }
2985 template<class T> template<Reg16 IXY> int CPUCore<T>::or_xix() {
2986  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
2987  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
2988  T::setMemPtr(addr);
2989  OR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
2990  return T::CC_DD + T::CC_CP_XIX;
2991 }
2992 
2993 // SBC A,r
2994 template<class T> inline void CPUCore<T>::SBC(byte reg) {
2995  unsigned res = getA() - reg - ((getF() & C_FLAG) ? 1 : 0);
2996  byte f = ((res & 0x100) ? C_FLAG : 0) |
2997  N_FLAG |
2998  ((getA() ^ res ^ reg) & H_FLAG) |
2999  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3000  if (T::isR800()) {
3001  f |= ZSTable[res & 0xFF];
3002  f |= getF() & (X_FLAG | Y_FLAG);
3003  } else {
3004  f |= ZSXYTable[res & 0xFF];
3005  }
3006  setF(f);
3007  setA(res);
3008 }
3009 template<class T> int CPUCore<T>::sbc_a_a() {
3010  if (T::isR800()) {
3011  word t = (getF() & C_FLAG)
3012  ? (255 * 256 | ZS255 | C_FLAG | H_FLAG | N_FLAG)
3013  : ( 0 * 256 | ZS0 | N_FLAG);
3014  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3015  } else {
3016  setAF((getF() & C_FLAG) ?
3017  (255 * 256 | ZSXY255 | C_FLAG | H_FLAG | N_FLAG) :
3018  ( 0 * 256 | ZSXY0 | N_FLAG));
3019  }
3020  return T::CC_CP_R;
3021 }
3022 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sbc_a_R() {
3023  SBC(get8<SRC>()); return T::CC_CP_R + EE;
3024 }
3025 template<class T> int CPUCore<T>::sbc_a_byte() {
3026  SBC(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3027 }
3028 template<class T> int CPUCore<T>::sbc_a_xhl() {
3029  SBC(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3030 }
3031 template<class T> template<Reg16 IXY> int CPUCore<T>::sbc_a_xix() {
3032  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3033  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3034  T::setMemPtr(addr);
3035  SBC(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3036  return T::CC_DD + T::CC_CP_XIX;
3037 }
3038 
3039 // SUB r
3040 template<class T> inline void CPUCore<T>::SUB(byte reg) {
3041  unsigned res = getA() - reg;
3042  byte f = ((res & 0x100) ? C_FLAG : 0) |
3043  N_FLAG |
3044  ((getA() ^ res ^ reg) & H_FLAG) |
3045  (((reg ^ getA()) & (getA() ^ res) & 0x80) >> 5); // V_FLAG
3046  if (T::isR800()) {
3047  f |= ZSTable[res & 0xFF];
3048  f |= getF() & (X_FLAG | Y_FLAG);
3049  } else {
3050  f |= ZSXYTable[res & 0xFF];
3051  }
3052  setF(f);
3053  setA(res);
3054 }
3055 template<class T> int CPUCore<T>::sub_a() {
3056  if (T::isR800()) {
3057  word t = 0 * 256 | ZS0 | N_FLAG;
3058  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3059  } else {
3060  setAF(0 * 256 | ZSXY0 | N_FLAG);
3061  }
3062  return T::CC_CP_R;
3063 }
3064 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::sub_R() {
3065  SUB(get8<SRC>()); return T::CC_CP_R + EE;
3066 }
3067 template<class T> int CPUCore<T>::sub_byte() {
3068  SUB(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3069 }
3070 template<class T> int CPUCore<T>::sub_xhl() {
3071  SUB(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3072 }
3073 template<class T> template<Reg16 IXY> int CPUCore<T>::sub_xix() {
3074  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3075  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3076  T::setMemPtr(addr);
3077  SUB(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3078  return T::CC_DD + T::CC_CP_XIX;
3079 }
3080 
3081 // XOR r
3082 template<class T> inline void CPUCore<T>::XOR(byte reg) {
3083  setA(getA() ^ reg);
3084  byte f = 0;
3085  if (T::isR800()) {
3086  f |= ZSPTable[getA()];
3087  f |= getF() & (X_FLAG | Y_FLAG);
3088  } else {
3089  f |= ZSPXYTable[getA()];
3090  }
3091  setF(f);
3092 }
3093 template<class T> int CPUCore<T>::xor_a() {
3094  if (T::isR800()) {
3095  word t = 0 * 256 + ZSP0;
3096  setAF(t | (getF() & (X_FLAG | Y_FLAG)));
3097  } else {
3098  setAF(0 * 256 + ZSPXY0);
3099  }
3100  return T::CC_CP_R;
3101 }
3102 template<class T> template<Reg8 SRC, int EE> int CPUCore<T>::xor_R() {
3103  XOR(get8<SRC>()); return T::CC_CP_R + EE;
3104 }
3105 template<class T> int CPUCore<T>::xor_byte() {
3106  XOR(RDMEM_OPCODE(T::CC_CP_N_1)); return T::CC_CP_N;
3107 }
3108 template<class T> int CPUCore<T>::xor_xhl() {
3109  XOR(RDMEM(getHL(), T::CC_CP_XHL_1)); return T::CC_CP_XHL;
3110 }
3111 template<class T> template<Reg16 IXY> int CPUCore<T>::xor_xix() {
3112  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_CP_XIX_1);
3113  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3114  T::setMemPtr(addr);
3115  XOR(RDMEM(addr, T::CC_DD + T::CC_CP_XIX_2));
3116  return T::CC_DD + T::CC_CP_XIX;
3117 }
3118 
3119 
3120 // DEC r
3121 template<class T> inline byte CPUCore<T>::DEC(byte reg) {
3122  byte res = reg - 1;
3123  byte f = ((reg & ~res & 0x80) >> 5) | // V_FLAG
3124  (((res & 0x0F) + 1) & H_FLAG) |
3125  N_FLAG;
3126  if (T::isR800()) {
3127  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3128  f |= ZSTable[res];
3129  } else {
3130  f |= getF() & C_FLAG;
3131  f |= ZSXYTable[res];
3132  }
3133  setF(f);
3134  return res;
3135 }
3136 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::dec_R() {
3137  set8<REG>(DEC(get8<REG>())); return T::CC_INC_R + EE;
3138 }
3139 template<class T> template<int EE> inline int CPUCore<T>::DEC_X(unsigned x) {
3140  byte val = DEC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3141  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3142  return T::CC_INC_XHL + EE;
3143 }
3144 template<class T> int CPUCore<T>::dec_xhl() {
3145  return DEC_X<0>(getHL());
3146 }
3147 template<class T> template<Reg16 IXY> int CPUCore<T>::dec_xix() {
3148  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3149  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3150  T::setMemPtr(addr);
3151  return DEC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3152 }
3153 
3154 // INC r
3155 template<class T> inline byte CPUCore<T>::INC(byte reg) {
3156  reg++;
3157  byte f = ((reg & -reg & 0x80) >> 5) | // V_FLAG
3158  (((reg & 0x0F) - 1) & H_FLAG) |
3159  0; // N_FLAG
3160  if (T::isR800()) {
3161  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3162  f |= ZSTable[reg];
3163  } else {
3164  f |= getF() & C_FLAG;
3165  f |= ZSXYTable[reg];
3166  }
3167  setF(f);
3168  return reg;
3169 }
3170 template<class T> template<Reg8 REG, int EE> int CPUCore<T>::inc_R() {
3171  set8<REG>(INC(get8<REG>())); return T::CC_INC_R + EE;
3172 }
3173 template<class T> template<int EE> inline int CPUCore<T>::INC_X(unsigned x) {
3174  byte val = INC(RDMEM(x, T::CC_INC_XHL_1 + EE));
3175  WRMEM(x, val, T::CC_INC_XHL_2 + EE);
3176  return T::CC_INC_XHL + EE;
3177 }
3178 template<class T> int CPUCore<T>::inc_xhl() {
3179  return INC_X<0>(getHL());
3180 }
3181 template<class T> template<Reg16 IXY> int CPUCore<T>::inc_xix() {
3182  int8_t ofst = RDMEM_OPCODE(T::CC_DD + T::CC_INC_XIX_1);
3183  unsigned addr = (get16<IXY>() + ofst) & 0xFFFF;
3184  T::setMemPtr(addr);
3185  return INC_X<T::CC_DD + T::EE_INC_XIX>(addr);
3186 }
3187 
3188 
3189 // ADC HL,ss
3190 template<class T> template<Reg16 REG> inline int CPUCore<T>::adc_hl_SS() {
3191  unsigned reg = get16<REG>();
3192  T::setMemPtr(getHL() + 1);
3193  unsigned res = getHL() + reg + ((getF() & C_FLAG) ? 1 : 0);
3194  byte f = (res >> 16) | // C_FLAG
3195  0; // N_FLAG
3196  if (T::isR800()) {
3197  f |= getF() & (X_FLAG | Y_FLAG);
3198  }
3199  if (res & 0xFFFF) {
3200  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3201  f |= 0; // Z_FLAG
3202  f |= ((getHL() ^ res) & (reg ^ res) & 0x8000) >> 13; // V_FLAG
3203  if (T::isR800()) {
3204  f |= (res >> 8) & S_FLAG;
3205  } else {
3206  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3207  }
3208  } else {
3209  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3210  f |= Z_FLAG;
3211  f |= (getHL() & reg & 0x8000) >> 13; // V_FLAG
3212  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3213  }
3214  setF(f);
3215  setHL(res);
3216  return T::CC_ADC_HL_SS;
3217 }
3218 template<class T> int CPUCore<T>::adc_hl_hl() {
3219  T::setMemPtr(getHL() + 1);
3220  unsigned res = 2 * getHL() + ((getF() & C_FLAG) ? 1 : 0);
3221  byte f = (res >> 16) | // C_FLAG
3222  0; // N_FLAG
3223  if (T::isR800()) {
3224  f |= getF() & (X_FLAG | Y_FLAG);
3225  }
3226  if (res & 0xFFFF) {
3227  f |= 0; // Z_FLAG
3228  f |= ((getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3229  if (T::isR800()) {
3230  f |= (res >> 8) & (H_FLAG | S_FLAG);
3231  } else {
3232  f |= (res >> 8) & (H_FLAG | S_FLAG | X_FLAG | Y_FLAG);
3233  }
3234  } else {
3235  f |= Z_FLAG;
3236  f |= (getHL() & 0x8000) >> 13; // V_FLAG
3237  f |= 0; // H_FLAG S_FLAG (X_FLAG Y_FLAG)
3238  }
3239  setF(f);
3240  setHL(res);
3241  return T::CC_ADC_HL_SS;
3242 }
3243 
3244 // ADD HL/IX/IY,ss
3245 template<class T> template<Reg16 REG1, Reg16 REG2, int EE> int CPUCore<T>::add_SS_TT() {
3246  unsigned reg1 = get16<REG1>();
3247  unsigned reg2 = get16<REG2>();
3248  T::setMemPtr(reg1 + 1);
3249  unsigned res = reg1 + reg2;
3250  byte f = (((reg1 ^ res ^ reg2) >> 8) & H_FLAG) |
3251  (res >> 16) | // C_FLAG
3252  0; // N_FLAG
3253  if (T::isR800()) {
3254  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3255  } else {
3256  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3257  f |= (res >> 8) & (X_FLAG | Y_FLAG);
3258  }
3259  setF(f);
3260  set16<REG1>(res & 0xFFFF);
3261  return T::CC_ADD_HL_SS + EE;
3262 }
3263 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::add_SS_SS() {
3264  unsigned reg = get16<REG>();
3265  T::setMemPtr(reg + 1);
3266  unsigned res = 2 * reg;
3267  byte f = (res >> 16) | // C_FLAG
3268  0; // N_FLAG
3269  if (T::isR800()) {
3270  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG | X_FLAG | Y_FLAG);
3271  f |= (res >> 8) & H_FLAG;
3272  } else {
3273  f |= getF() & (S_FLAG | Z_FLAG | V_FLAG);
3274  f |= (res >> 8) & (H_FLAG | X_FLAG | Y_FLAG);
3275  }
3276  setF(f);
3277  set16<REG>(res & 0xFFFF);
3278  return T::CC_ADD_HL_SS + EE;
3279 }
3280 
3281 // SBC HL,ss
3282 template<class T> template<Reg16 REG> inline int CPUCore<T>::sbc_hl_SS() {
3283  unsigned reg = get16<REG>();
3284  T::setMemPtr(getHL() + 1);
3285  unsigned res = getHL() - reg - ((getF() & C_FLAG) ? 1 : 0);
3286  byte f = ((res & 0x10000) ? C_FLAG : 0) |
3287  N_FLAG;
3288  if (T::isR800()) {
3289  f |= getF() & (X_FLAG | Y_FLAG);
3290  }
3291  if (res & 0xFFFF) {
3292  f |= ((getHL() ^ res ^ reg) >> 8) & H_FLAG;
3293  f |= 0; // Z_FLAG
3294  f |= ((reg ^ getHL()) & (getHL() ^ res) & 0x8000) >> 13; // V_FLAG
3295  if (T::isR800()) {
3296  f |= (res >> 8) & S_FLAG;
3297  } else {
3298  f |= (res >> 8) & (S_FLAG | X_FLAG | Y_FLAG);
3299  }
3300  } else {
3301  f |= ((getHL() ^ reg) >> 8) & H_FLAG;
3302  f |= Z_FLAG;
3303  f |= ((reg ^ getHL()) & getHL() & 0x8000) >> 13; // V_FLAG
3304  f |= 0; // S_FLAG (X_FLAG Y_FLAG)
3305  }
3306  setF(f);
3307  setHL(res);
3308  return T::CC_ADC_HL_SS;
3309 }
3310 template<class T> int CPUCore<T>::sbc_hl_hl() {
3311  T::setMemPtr(getHL() + 1);
3312  byte f = T::isR800() ? (getF() & (X_FLAG | Y_FLAG)) : 0;
3313  if (getF() & C_FLAG) {
3314  f |= C_FLAG | H_FLAG | S_FLAG | N_FLAG;
3315  if (!T::isR800()) {
3316  f |= X_FLAG | Y_FLAG;
3317  }
3318  setHL(0xFFFF);
3319  } else {
3320  f |= Z_FLAG | N_FLAG;
3321  setHL(0);
3322  }
3323  setF(f);
3324  return T::CC_ADC_HL_SS;
3325 }
3326 
3327 // DEC ss
3328 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::dec_SS() {
3329  set16<REG>(get16<REG>() - 1); return T::CC_INC_SS + EE;
3330 }
3331 
3332 // INC ss
3333 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::inc_SS() {
3334  set16<REG>(get16<REG>() + 1); return T::CC_INC_SS + EE;
3335 }
3336 
3337 
3338 // BIT n,r
3339 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::bit_N_R() {
3340  byte reg = get8<REG>();
3341  byte f = 0; // N_FLAG
3342  if (T::isR800()) {
3343  // this is very different from Z80 (not only XY flags)
3344  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3345  f |= H_FLAG;
3346  f |= (reg & (1 << N)) ? 0 : Z_FLAG;
3347  } else {
3348  f |= ZSPHTable[reg & (1 << N)];
3349  f |= getF() & C_FLAG;
3350  f |= reg & (X_FLAG | Y_FLAG);
3351  }
3352  setF(f);
3353  return T::CC_BIT_R;
3354 }
3355 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xhl() {
3356  byte m = RDMEM(getHL(), T::CC_BIT_XHL_1) & (1 << N);
3357  byte f = 0; // N_FLAG
3358  if (T::isR800()) {
3359  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3360  f |= H_FLAG;
3361  f |= m ? 0 : Z_FLAG;
3362  } else {
3363  f |= ZSPHTable[m];
3364  f |= getF() & C_FLAG;
3365  f |= (T::getMemPtr() >> 8) & (X_FLAG | Y_FLAG);
3366  }
3367  setF(f);
3368  return T::CC_BIT_XHL;
3369 }
3370 template<class T> template<unsigned N> inline int CPUCore<T>::bit_N_xix(unsigned addr) {
3371  T::setMemPtr(addr);
3372  byte m = RDMEM(addr, T::CC_DD + T::CC_BIT_XIX_1) & (1 << N);
3373  byte f = 0; // N_FLAG
3374  if (T::isR800()) {
3375  f |= getF() & (S_FLAG | V_FLAG | C_FLAG | X_FLAG | Y_FLAG);
3376  f |= H_FLAG;
3377  f |= m ? 0 : Z_FLAG;
3378  } else {
3379  f |= ZSPHTable[m];
3380  f |= getF() & C_FLAG;
3381  f |= (addr >> 8) & (X_FLAG | Y_FLAG);
3382  }
3383  setF(f);
3384  return T::CC_DD + T::CC_BIT_XIX;
3385 }
3386 
3387 // RES n,r
3388 static inline byte RES(unsigned b, byte reg) {
3389  return reg & ~(1 << b);
3390 }
3391 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_R() {
3392  set8<REG>(RES(N, get8<REG>())); return T::CC_SET_R;
3393 }
3394 template<class T> template<int EE> inline byte CPUCore<T>::RES_X(unsigned bit, unsigned addr) {
3395  byte res = RES(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3396  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3397  return res;
3398 }
3399 template<class T> template<unsigned N> int CPUCore<T>::res_N_xhl() {
3400  RES_X<0>(N, getHL()); return T::CC_SET_XHL;
3401 }
3402 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::res_N_xix_R(unsigned a) {
3403  T::setMemPtr(a);
3404  set8<REG>(RES_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3405  return T::CC_DD + T::CC_SET_XIX;
3406 }
3407 
3408 // SET n,r
3409 static inline byte SET(unsigned b, byte reg) {
3410  return reg | (1 << b);
3411 }
3412 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_R() {
3413  set8<REG>(SET(N, get8<REG>())); return T::CC_SET_R;
3414 }
3415 template<class T> template<int EE> inline byte CPUCore<T>::SET_X(unsigned bit, unsigned addr) {
3416  byte res = SET(bit, RDMEM(addr, T::CC_SET_XHL_1 + EE));
3417  WRMEM(addr, res, T::CC_SET_XHL_2 + EE);
3418  return res;
3419 }
3420 template<class T> template<unsigned N> int CPUCore<T>::set_N_xhl() {
3421  SET_X<0>(N, getHL()); return T::CC_SET_XHL;
3422 }
3423 template<class T> template<unsigned N, Reg8 REG> int CPUCore<T>::set_N_xix_R(unsigned a) {
3424  T::setMemPtr(a);
3425  set8<REG>(SET_X<T::CC_DD + T::EE_SET_XIX>(N, a));
3426  return T::CC_DD + T::CC_SET_XIX;
3427 }
3428 
3429 // RL r
3430 template<class T> inline byte CPUCore<T>::RL(byte reg) {
3431  byte c = reg >> 7;
3432  reg = (reg << 1) | ((getF() & C_FLAG) ? 0x01 : 0);
3433  byte f = c ? C_FLAG : 0;
3434  if (T::isR800()) {
3435  f |= ZSPTable[reg];
3436  f |= getF() & (X_FLAG | Y_FLAG);
3437  } else {
3438  f |= ZSPXYTable[reg];
3439  }
3440  setF(f);
3441  return reg;
3442 }
3443 template<class T> template<int EE> inline byte CPUCore<T>::RL_X(unsigned x) {
3444  byte res = RL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3445  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3446  return res;
3447 }
3448 template<class T> template<Reg8 REG> int CPUCore<T>::rl_R() {
3449  set8<REG>(RL(get8<REG>())); return T::CC_SET_R;
3450 }
3451 template<class T> int CPUCore<T>::rl_xhl() {
3452  RL_X<0>(getHL()); return T::CC_SET_XHL;
3453 }
3454 template<class T> template<Reg8 REG> int CPUCore<T>::rl_xix_R(unsigned a) {
3455  T::setMemPtr(a);
3456  set8<REG>(RL_X<T::CC_DD + T::EE_SET_XIX>(a));
3457  return T::CC_DD + T::CC_SET_XIX;
3458 }
3459 
3460 // RLC r
3461 template<class T> inline byte CPUCore<T>::RLC(byte reg) {
3462  byte c = reg >> 7;
3463  reg = (reg << 1) | c;
3464  byte f = c ? C_FLAG : 0;
3465  if (T::isR800()) {
3466  f |= ZSPTable[reg];
3467  f |= getF() & (X_FLAG | Y_FLAG);
3468  } else {
3469  f |= ZSPXYTable[reg];
3470  }
3471  setF(f);
3472  return reg;
3473 }
3474 template<class T> template<int EE> inline byte CPUCore<T>::RLC_X(unsigned x) {
3475  byte res = RLC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3476  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3477  return res;
3478 }
3479 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_R() {
3480  set8<REG>(RLC(get8<REG>())); return T::CC_SET_R;
3481 }
3482 template<class T> int CPUCore<T>::rlc_xhl() {
3483  RLC_X<0>(getHL()); return T::CC_SET_XHL;
3484 }
3485 template<class T> template<Reg8 REG> int CPUCore<T>::rlc_xix_R(unsigned a) {
3486  T::setMemPtr(a);
3487  set8<REG>(RLC_X<T::CC_DD + T::EE_SET_XIX>(a));
3488  return T::CC_DD + T::CC_SET_XIX;
3489 }
3490 
3491 // RR r
3492 template<class T> inline byte CPUCore<T>::RR(byte reg) {
3493  byte c = reg & 1;
3494  reg = (reg >> 1) | ((getF() & C_FLAG) << 7);
3495  byte f = c ? C_FLAG : 0;
3496  if (T::isR800()) {
3497  f |= ZSPTable[reg];
3498  f |= getF() & (X_FLAG | Y_FLAG);
3499  } else {
3500  f |= ZSPXYTable[reg];
3501  }
3502  setF(f);
3503  return reg;
3504 }
3505 template<class T> template<int EE> inline byte CPUCore<T>::RR_X(unsigned x) {
3506  byte res = RR(RDMEM(x, T::CC_SET_XHL_1 + EE));
3507  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3508  return res;
3509 }
3510 template<class T> template<Reg8 REG> int CPUCore<T>::rr_R() {
3511  set8<REG>(RR(get8<REG>())); return T::CC_SET_R;
3512 }
3513 template<class T> int CPUCore<T>::rr_xhl() {
3514  RR_X<0>(getHL()); return T::CC_SET_XHL;
3515 }
3516 template<class T> template<Reg8 REG> int CPUCore<T>::rr_xix_R(unsigned a) {
3517  T::setMemPtr(a);
3518  set8<REG>(RR_X<T::CC_DD + T::EE_SET_XIX>(a));
3519  return T::CC_DD + T::CC_SET_XIX;
3520 }
3521 
3522 // RRC r
3523 template<class T> inline byte CPUCore<T>::RRC(byte reg) {
3524  byte c = reg & 1;
3525  reg = (reg >> 1) | (c << 7);
3526  byte f = c ? C_FLAG : 0;
3527  if (T::isR800()) {
3528  f |= ZSPTable[reg];
3529  f |= getF() & (X_FLAG | Y_FLAG);
3530  } else {
3531  f |= ZSPXYTable[reg];
3532  }
3533  setF(f);
3534  return reg;
3535 }
3536 template<class T> template<int EE> inline byte CPUCore<T>::RRC_X(unsigned x) {
3537  byte res = RRC(RDMEM(x, T::CC_SET_XHL_1 + EE));
3538  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3539  return res;
3540 }
3541 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_R() {
3542  set8<REG>(RRC(get8<REG>())); return T::CC_SET_R;
3543 }
3544 template<class T> int CPUCore<T>::rrc_xhl() {
3545  RRC_X<0>(getHL()); return T::CC_SET_XHL;
3546 }
3547 template<class T> template<Reg8 REG> int CPUCore<T>::rrc_xix_R(unsigned a) {
3548  T::setMemPtr(a);
3549  set8<REG>(RRC_X<T::CC_DD + T::EE_SET_XIX>(a));
3550  return T::CC_DD + T::CC_SET_XIX;
3551 }
3552 
3553 // SLA r
3554 template<class T> inline byte CPUCore<T>::SLA(byte reg) {
3555  byte c = reg >> 7;
3556  reg <<= 1;
3557  byte f = c ? C_FLAG : 0;
3558  if (T::isR800()) {
3559  f |= ZSPTable[reg];
3560  f |= getF() & (X_FLAG | Y_FLAG);
3561  } else {
3562  f |= ZSPXYTable[reg];
3563  }
3564  setF(f);
3565  return reg;
3566 }
3567 template<class T> template<int EE> inline byte CPUCore<T>::SLA_X(unsigned x) {
3568  byte res = SLA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3569  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3570  return res;
3571 }
3572 template<class T> template<Reg8 REG> int CPUCore<T>::sla_R() {
3573  set8<REG>(SLA(get8<REG>())); return T::CC_SET_R;
3574 }
3575 template<class T> int CPUCore<T>::sla_xhl() {
3576  SLA_X<0>(getHL()); return T::CC_SET_XHL;
3577 }
3578 template<class T> template<Reg8 REG> int CPUCore<T>::sla_xix_R(unsigned a) {
3579  T::setMemPtr(a);
3580  set8<REG>(SLA_X<T::CC_DD + T::EE_SET_XIX>(a));
3581  return T::CC_DD + T::CC_SET_XIX;
3582 }
3583 
3584 // SLL r
3585 template<class T> inline byte CPUCore<T>::SLL(byte reg) {
3586  assert(!T::isR800()); // this instruction is Z80-only
3587  byte c = reg >> 7;
3588  reg = (reg << 1) | 1;
3589  byte f = c ? C_FLAG : 0;
3590  f |= ZSPXYTable[reg];
3591  setF(f);
3592  return reg;
3593 }
3594 template<class T> template<int EE> inline byte CPUCore<T>::SLL_X(unsigned x) {
3595  byte res = SLL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3596  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3597  return res;
3598 }
3599 template<class T> template<Reg8 REG> int CPUCore<T>::sll_R() {
3600  set8<REG>(SLL(get8<REG>())); return T::CC_SET_R;
3601 }
3602 template<class T> int CPUCore<T>::sll_xhl() {
3603  SLL_X<0>(getHL()); return T::CC_SET_XHL;
3604 }
3605 template<class T> template<Reg8 REG> int CPUCore<T>::sll_xix_R(unsigned a) {
3606  T::setMemPtr(a);
3607  set8<REG>(SLL_X<T::CC_DD + T::EE_SET_XIX>(a));
3608  return T::CC_DD + T::CC_SET_XIX;
3609 }
3610 template<class T> int CPUCore<T>::sll2() {
3611  assert(T::isR800()); // this instruction is R800-only
3612  byte f = (getF() & (X_FLAG | Y_FLAG)) |
3613  (getA() >> 7) | // C_FLAG
3614  0; // all other flags zero
3615  setF(f);
3616  return T::CC_DD + T::CC_SET_XIX; // TODO
3617 }
3618 
3619 // SRA r
3620 template<class T> inline byte CPUCore<T>::SRA(byte reg) {
3621  byte c = reg & 1;
3622  reg = (reg >> 1) | (reg & 0x80);
3623  byte f = c ? C_FLAG : 0;
3624  if (T::isR800()) {
3625  f |= ZSPTable[reg];
3626  f |= getF() & (X_FLAG | Y_FLAG);
3627  } else {
3628  f |= ZSPXYTable[reg];
3629  }
3630  setF(f);
3631  return reg;
3632 }
3633 template<class T> template<int EE> inline byte CPUCore<T>::SRA_X(unsigned x) {
3634  byte res = SRA(RDMEM(x, T::CC_SET_XHL_1 + EE));
3635  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3636  return res;
3637 }
3638 template<class T> template<Reg8 REG> int CPUCore<T>::sra_R() {
3639  set8<REG>(SRA(get8<REG>())); return T::CC_SET_R;
3640 }
3641 template<class T> int CPUCore<T>::sra_xhl() {
3642  SRA_X<0>(getHL()); return T::CC_SET_XHL;
3643 }
3644 template<class T> template<Reg8 REG> int CPUCore<T>::sra_xix_R(unsigned a) {
3645  T::setMemPtr(a);
3646  set8<REG>(SRA_X<T::CC_DD + T::EE_SET_XIX>(a));
3647  return T::CC_DD + T::CC_SET_XIX;
3648 }
3649 
3650 // SRL R
3651 template<class T> inline byte CPUCore<T>::SRL(byte reg) {
3652  byte c = reg & 1;
3653  reg >>= 1;
3654  byte f = c ? C_FLAG : 0;
3655  if (T::isR800()) {
3656  f |= ZSPTable[reg];
3657  f |= getF() & (X_FLAG | Y_FLAG);
3658  } else {
3659  f |= ZSPXYTable[reg];
3660  }
3661  setF(f);
3662  return reg;
3663 }
3664 template<class T> template<int EE> inline byte CPUCore<T>::SRL_X(unsigned x) {
3665  byte res = SRL(RDMEM(x, T::CC_SET_XHL_1 + EE));
3666  WRMEM(x, res, T::CC_SET_XHL_2 + EE);
3667  return res;
3668 }
3669 template<class T> template<Reg8 REG> int CPUCore<T>::srl_R() {
3670  set8<REG>(SRL(get8<REG>())); return T::CC_SET_R;
3671 }
3672 template<class T> int CPUCore<T>::srl_xhl() {
3673  SRL_X<0>(getHL()); return T::CC_SET_XHL;
3674 }
3675 template<class T> template<Reg8 REG> int CPUCore<T>::srl_xix_R(unsigned a) {
3676  T::setMemPtr(a);
3677  set8<REG>(SRL_X<T::CC_DD + T::EE_SET_XIX>(a));
3678  return T::CC_DD + T::CC_SET_XIX;
3679 }
3680 
3681 // RLA RLCA RRA RRCA
3682 template<class T> int CPUCore<T>::rla() {
3683  byte c = getF() & C_FLAG;
3684  byte f = (getA() & 0x80) ? C_FLAG : 0;
3685  if (T::isR800()) {
3686  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3687  } else {
3688  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3689  }
3690  setA((getA() << 1) | (c ? 1 : 0));
3691  if (!T::isR800()) {
3692  f |= getA() & (X_FLAG | Y_FLAG);
3693  }
3694  setF(f);
3695  return T::CC_RLA;
3696 }
3697 template<class T> int CPUCore<T>::rlca() {
3698  setA((getA() << 1) | (getA() >> 7));
3699  byte f = 0;
3700  if (T::isR800()) {
3701  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3702  f |= getA() & C_FLAG;
3703  } else {
3704  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3705  f |= getA() & (Y_FLAG | X_FLAG | C_FLAG);
3706  }
3707  setF(f);
3708  return T::CC_RLA;
3709 }
3710 template<class T> int CPUCore<T>::rra() {
3711  byte c = (getF() & C_FLAG) << 7;
3712  byte f = (getA() & 0x01) ? C_FLAG : 0;
3713  if (T::isR800()) {
3714  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3715  } else {
3716  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3717  }
3718  setA((getA() >> 1) | c);
3719  if (!T::isR800()) {
3720  f |= getA() & (X_FLAG | Y_FLAG);
3721  }
3722  setF(f);
3723  return T::CC_RLA;
3724 }
3725 template<class T> int CPUCore<T>::rrca() {
3726  byte f = getA() & C_FLAG;
3727  if (T::isR800()) {
3728  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
3729  } else {
3730  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
3731  }
3732  setA((getA() >> 1) | (getA() << 7));
3733  if (!T::isR800()) {
3734  f |= getA() & (X_FLAG | Y_FLAG);
3735  }
3736  setF(f);
3737  return T::CC_RLA;
3738 }
3739 
3740 
3741 // RLD
3742 template<class T> int CPUCore<T>::rld() {
3743  byte val = RDMEM(getHL(), T::CC_RLD_1);
3744  T::setMemPtr(getHL() + 1);
3745  WRMEM(getHL(), (val << 4) | (getA() & 0x0F), T::CC_RLD_2);
3746  setA((getA() & 0xF0) | (val >> 4));
3747  byte f = 0;
3748  if (T::isR800()) {
3749  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3750  f |= ZSPTable[getA()];
3751  } else {
3752  f |= getF() & C_FLAG;
3753  f |= ZSPXYTable[getA()];
3754  }
3755  setF(f);
3756  return T::CC_RLD;
3757 }
3758 
3759 // RRD
3760 template<class T> int CPUCore<T>::rrd() {
3761  byte val = RDMEM(getHL(), T::CC_RLD_1);
3762  T::setMemPtr(getHL() + 1);
3763  WRMEM(getHL(), (val >> 4) | (getA() << 4), T::CC_RLD_2);
3764  setA((getA() & 0xF0) | (val & 0x0F));
3765  byte f = 0;
3766  if (T::isR800()) {
3767  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3768  f |= ZSPTable[getA()];
3769  } else {
3770  f |= getF() & C_FLAG;
3771  f |= ZSPXYTable[getA()];
3772  }
3773  setF(f);
3774  return T::CC_RLD;
3775 }
3776 
3777 
3778 // PUSH ss
3779 template<class T> template<int EE> inline void CPUCore<T>::PUSH(unsigned reg) {
3780  setSP(getSP() - 2);
3781  WR_WORD_rev<true, true>(getSP(), reg, T::CC_PUSH_1 + EE);
3782 }
3783 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::push_SS() {
3784  PUSH<EE>(get16<REG>()); return T::CC_PUSH + EE;
3785 }
3786 
3787 // POP ss
3788 template<class T> template<int EE> inline unsigned CPUCore<T>::POP() {
3789  unsigned addr = getSP();
3790  setSP(addr + 2);
3791  return RD_WORD(addr, T::CC_POP_1 + EE);
3792 }
3793 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::pop_SS() {
3794  set16<REG>(POP<EE>()); return T::CC_POP + EE;
3795 }
3796 
3797 
3798 // CALL nn / CALL cc,nn
3799 template<class T> template<typename COND> int CPUCore<T>::call(COND cond) {
3800  unsigned addr = RD_WORD_PC(T::CC_CALL_1);
3801  T::setMemPtr(addr);
3802  if (cond(getF())) {
3803  PUSH<T::EE_CALL>(getPC());
3804  setPC(addr);
3805  return T::CC_CALL_A;
3806  } else {
3807  return T::CC_CALL_B;
3808  }
3809 }
3810 
3811 
3812 // RST n
3813 template<class T> template<unsigned ADDR> int CPUCore<T>::rst() {
3814  PUSH<0>(getPC());
3815  T::setMemPtr(ADDR);
3816  setPC(ADDR);
3817  return T::CC_RST;
3818 }
3819 
3820 
3821 // RET
3822 template<class T> template<int EE, typename COND> inline int CPUCore<T>::RET(COND cond) {
3823  if (cond(getF())) {
3824  unsigned addr = POP<EE>();
3825  T::setMemPtr(addr);
3826  setPC(addr);
3827  return T::CC_RET_A + EE;
3828  } else {
3829  return T::CC_RET_B + EE;
3830  }
3831 }
3832 template<class T> template<typename COND> int CPUCore<T>::ret(COND cond) {
3833  return RET<T::EE_RET_C>(cond);
3834 }
3835 template<class T> int CPUCore<T>::ret() {
3836  return RET<0>(CondTrue());
3837 }
3838 template<class T> int CPUCore<T>::retn() { // also reti
3839  setIFF1(getIFF2());
3840  setSlowInstructions();
3841  return RET<T::EE_RETN>(CondTrue());
3842 }
3843 
3844 
3845 // JP ss
3846 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::jp_SS() {
3847  setPC(get16<REG>()); T::R800ForcePageBreak(); return T::CC_JP_HL + EE;
3848 }
3849 
3850 // JP nn / JP cc,nn
3851 template<class T> template<typename COND> int CPUCore<T>::jp(COND cond) {
3852  unsigned addr = RD_WORD_PC(T::CC_JP_1);
3853  T::setMemPtr(addr);
3854  if (cond(getF())) {
3855  setPC(addr);
3856  T::R800ForcePageBreak();
3857  return T::CC_JP_A;
3858  } else {
3859  return T::CC_JP_B;
3860  }
3861 }
3862 
3863 // JR e
3864 template<class T> template<typename COND> int CPUCore<T>::jr(COND cond) {
3865  int8_t ofst = RDMEM_OPCODE(T::CC_JR_1);
3866  if (cond(getF())) {
3867  if ((getPC() & 0xFF) == 0) {
3868  // On R800, when this instruction is located in the
3869  // last two byte of a page (a page is a 256-byte
3870  // (aligned) memory block) and even if we jump back,
3871  // thus fetching the next opcode byte does not cause a
3872  // page-break, there still is one cycle overhead. It's
3873  // as-if there is a page-break.
3874  //
3875  // This could be explained by some (very limited)
3876  // pipeline behaviour in R800: it seems that the
3877  // decision to cause a page-break on the next
3878  // instruction is already made before the jump
3879  // destination address for the current instruction is
3880  // calculated (though a destination address in another
3881  // page is also a reason for a page-break).
3882  //
3883  // It's likely all instructions behave like this, but I
3884  // think we can get away with only explicitly emulating
3885  // this behaviour in the djnz and the jr (conditional
3886  // or not) instructions: all other instructions that
3887  // cause the PC to change in a non-incremental way do
3888  // already force a pagebreak for another reason, so
3889  // this effect is masked. Examples of such instructions
3890  // are: JP, RET, CALL, RST, all repeated block
3891  // instructions, accepting an IRQ, (are there more
3892  // instructions are events that change PC?)
3893  //
3894  // See doc/r800-djnz.txt for more details.
3895  T::R800ForcePageBreak();
3896  }
3897  setPC((getPC() + ofst) & 0xFFFF);
3898  T::setMemPtr(getPC());
3899  return T::CC_JR_A;
3900  } else {
3901  return T::CC_JR_B;
3902  }
3903 }
3904 
3905 // DJNZ e
3906 template<class T> int CPUCore<T>::djnz() {
3907  byte b = getB() - 1;
3908  setB(b);
3909  int8_t ofst = RDMEM_OPCODE(T::CC_JR_1 + T::EE_DJNZ);
3910  if (b) {
3911  if ((getPC() & 0xFF) == 0) {
3912  // See comment in jr()
3913  T::R800ForcePageBreak();
3914  }
3915  setPC((getPC() + ofst) & 0xFFFF);
3916  T::setMemPtr(getPC());
3917  return T::CC_JR_A + T::EE_DJNZ;
3918  } else {
3919  return T::CC_JR_B + T::EE_DJNZ;
3920  }
3921 }
3922 
3923 // EX (SP),ss
3924 template<class T> template<Reg16 REG, int EE> int CPUCore<T>::ex_xsp_SS() {
3925  unsigned res = RD_WORD_impl<true, false>(getSP(), T::CC_EX_SP_HL_1 + EE);
3926  T::setMemPtr(res);
3927  WR_WORD_rev<false, true>(getSP(), get16<REG>(), T::CC_EX_SP_HL_2 + EE);
3928  set16<REG>(res);
3929  return T::CC_EX_SP_HL + EE;
3930 }
3931 
3932 // IN r,(c)
3933 template<class T> template<Reg8 REG> int CPUCore<T>::in_R_c() {
3934  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_R_C_1);
3935  T::setMemPtr(getBC() + 1);
3936  byte res = READ_PORT(getBC(), T::CC_IN_R_C_1);
3937  byte f = 0;
3938  if (T::isR800()) {
3939  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3940  f |= ZSPTable[res];
3941  } else {
3942  f |= getF() & C_FLAG;
3943  f |= ZSPXYTable[res];
3944  }
3945  setF(f);
3946  set8<REG>(res);
3947  return T::CC_IN_R_C;
3948 }
3949 
3950 // IN a,(n)
3951 template<class T> int CPUCore<T>::in_a_byte() {
3952  unsigned y = RDMEM_OPCODE(T::CC_IN_A_N_1) + 256 * getA();
3953  T::setMemPtr(y + 1);
3954  if (T::isR800()) T::waitForEvenCycle(T::CC_IN_A_N_2);
3955  setA(READ_PORT(y, T::CC_IN_A_N_2));
3956  return T::CC_IN_A_N;
3957 }
3958 
3959 // OUT (c),r
3960 template<class T> template<Reg8 REG> int CPUCore<T>::out_c_R() {
3961  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3962  T::setMemPtr(getBC() + 1);
3963  WRITE_PORT(getBC(), get8<REG>(), T::CC_OUT_C_R_1);
3964  return T::CC_OUT_C_R;
3965 }
3966 template<class T> int CPUCore<T>::out_c_0() {
3967  // TODO not on R800
3968  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_C_R_1);
3969  T::setMemPtr(getBC() + 1);
3970  byte out_c_x = isTurboR ? 255 : 0;
3971  WRITE_PORT(getBC(), out_c_x, T::CC_OUT_C_R_1);
3972  return T::CC_OUT_C_R;
3973 }
3974 
3975 // OUT (n),a
3976 template<class T> int CPUCore<T>::out_byte_a() {
3977  byte port = RDMEM_OPCODE(T::CC_OUT_N_A_1);
3978  unsigned y = (getA() << 8) | port;
3979  T::setMemPtr((getA() << 8) | ((port + 1) & 255));
3980  if (T::isR800()) T::waitForEvenCycle(T::CC_OUT_N_A_2);
3981  WRITE_PORT(y, getA(), T::CC_OUT_N_A_2);
3982  return T::CC_OUT_N_A;
3983 }
3984 
3985 
3986 // block CP
3987 template<class T> inline int CPUCore<T>::BLOCK_CP(int increase, bool repeat) {
3988  T::setMemPtr(T::getMemPtr() + increase);
3989  byte val = RDMEM(getHL(), T::CC_CPI_1);
3990  byte res = getA() - val;
3991  setHL(getHL() + increase);
3992  setBC(getBC() - 1);
3993  byte f = ((getA() ^ val ^ res) & H_FLAG) |
3994  ZSTable[res] |
3995  N_FLAG |
3996  (getBC() ? V_FLAG : 0);
3997  if (T::isR800()) {
3998  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
3999  } else {
4000  f |= getF() & C_FLAG;
4001  unsigned k = res - ((f & H_FLAG) >> 4);
4002  f |= (k << 4) & Y_FLAG; // bit 1 -> flag 5
4003  f |= k & X_FLAG; // bit 3 -> flag 3
4004  }
4005  setF(f);
4006  if (repeat && getBC() && res) {
4007  setPC(getPC() - 2);
4008  T::setMemPtr(getPC() + 1);
4009  return T::CC_CPIR;
4010  } else {
4011  return T::CC_CPI;
4012  }
4013 }
4014 template<class T> int CPUCore<T>::cpd() { return BLOCK_CP(-1, false); }
4015 template<class T> int CPUCore<T>::cpi() { return BLOCK_CP( 1, false); }
4016 template<class T> int CPUCore<T>::cpdr() { return BLOCK_CP(-1, true ); }
4017 template<class T> int CPUCore<T>::cpir() { return BLOCK_CP( 1, true ); }
4018 
4019 
4020 // block LD
4021 template<class T> inline int CPUCore<T>::BLOCK_LD(int increase, bool repeat) {
4022  byte val = RDMEM(getHL(), T::CC_LDI_1);
4023  WRMEM(getDE(), val, T::CC_LDI_2);
4024  setHL(getHL() + increase);
4025  setDE(getDE() + increase);
4026  setBC(getBC() - 1);
4027  byte f = getBC() ? V_FLAG : 0;
4028  if (T::isR800()) {
4029  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG | X_FLAG | Y_FLAG);
4030  } else {
4031  f |= getF() & (S_FLAG | Z_FLAG | C_FLAG);
4032  f |= ((getA() + val) << 4) & Y_FLAG; // bit 1 -> flag 5
4033  f |= (getA() + val) & X_FLAG; // bit 3 -> flag 3
4034  }
4035  setF(f);
4036  if (repeat && getBC()) {
4037  setPC(getPC() - 2);
4038  T::setMemPtr(getPC() + 1);
4039  return T::CC_LDIR;
4040  } else {
4041  return T::CC_LDI;
4042  }
4043 }
4044 template<class T> int CPUCore<T>::ldd() { return BLOCK_LD(-1, false); }
4045 template<class T> int CPUCore<T>::ldi() { return BLOCK_LD( 1, false); }
4046 template<class T> int CPUCore<T>::lddr() { return BLOCK_LD(-1, true ); }
4047 template<class T> int CPUCore<T>::ldir() { return BLOCK_LD( 1, true ); }
4048 
4049 
4050 // block IN
4051 template<class T> inline int CPUCore<T>::BLOCK_IN(int increase, bool repeat) {
4052  // TODO R800 flags
4053  if (T::isR800()) T::waitForEvenCycle(T::CC_INI_1);
4054  T::setMemPtr(getBC() + increase);
4055  setBC(getBC() - 0x100); // decr before use
4056  byte val = READ_PORT(getBC(), T::CC_INI_1);
4057  WRMEM(getHL(), val, T::CC_INI_2);
4058  setHL(getHL() + increase);
4059  unsigned k = val + ((getC() + increase) & 0xFF);
4060  byte b = getB();
4061  setF(((val & S_FLAG) >> 6) | // N_FLAG
4062  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4063  ZSXYTable[b] |
4064  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4065  if (repeat && b) {
4066  setPC(getPC() - 2);
4067  return T::CC_INIR;
4068  } else {
4069  return T::CC_INI;
4070  }
4071 }
4072 template<class T> int CPUCore<T>::ind() { return BLOCK_IN(-1, false); }
4073 template<class T> int CPUCore<T>::ini() { return BLOCK_IN( 1, false); }
4074 template<class T> int CPUCore<T>::indr() { return BLOCK_IN(-1, true ); }
4075 template<class T> int CPUCore<T>::inir() { return BLOCK_IN( 1, true ); }
4076 
4077 
4078 // block OUT
4079 template<class T> inline int CPUCore<T>::BLOCK_OUT(int increase, bool repeat) {
4080  // TODO R800 flags
4081  byte val = RDMEM(getHL(), T::CC_OUTI_1);
4082  setHL(getHL() + increase);
4083  if (T::isR800()) T::waitForEvenCycle(T::CC_OUTI_2);
4084  WRITE_PORT(getBC(), val, T::CC_OUTI_2);
4085  setBC(getBC() - 0x100); // decr after use
4086  T::setMemPtr(getBC() + increase);
4087  unsigned k = val + getL();
4088  byte b = getB();
4089  setF(((val & S_FLAG) >> 6) | // N_FLAG
4090  ((k & 0x100) ? (H_FLAG | C_FLAG) : 0) |
4091  ZSXYTable[b] |
4092  (ZSPXYTable[(k & 0x07) ^ b] & P_FLAG));
4093  if (repeat && b) {
4094  setPC(getPC() - 2);
4095  return T::CC_OTIR;
4096  } else {
4097  return T::CC_OUTI;
4098  }
4099 }
4100 template<class T> int CPUCore<T>::outd() { return BLOCK_OUT(-1, false); }
4101 template<class T> int CPUCore<T>::outi() { return BLOCK_OUT( 1, false); }
4102 template<class T> int CPUCore<T>::otdr() { return BLOCK_OUT(-1, true ); }
4103 template<class T> int CPUCore<T>::otir() { return BLOCK_OUT( 1, true ); }
4104 
4105 
4106 // various
4107 template<class T> int CPUCore<T>::nop() { return T::CC_NOP; }
4108 template<class T> int CPUCore<T>::ccf() {
4109  byte f = 0;
4110  if (T::isR800()) {
4111  // H flag is different from Z80 (and as always XY flags as well)
4112  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | X_FLAG | Y_FLAG | H_FLAG);
4113  } else {
4114  f |= (getF() & C_FLAG) << 4; // H_FLAG
4115  // only set X(Y) flag (don't reset if already set)
4116  if (isTurboR) {
4117  // Y flag is not changed on a turboR-Z80
4118  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG | Y_FLAG);
4119  f |= (getF() | getA()) & X_FLAG;
4120  } else {
4121  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4122  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4123  }
4124  }
4125  f ^= C_FLAG;
4126  setF(f);
4127  return T::CC_CCF;
4128 }
4129 template<class T> int CPUCore<T>::cpl() {
4130  setA(getA() ^ 0xFF);
4131  byte f = H_FLAG | N_FLAG;
4132  if (T::isR800()) {
4133  f |= getF();
4134  } else {
4135  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | C_FLAG);
4136  f |= getA() & (X_FLAG | Y_FLAG);
4137  }
4138  setF(f);
4139  return T::CC_CPL;
4140 }
4141 template<class T> int CPUCore<T>::daa() {
4142  byte a = getA();
4143  byte f = getF();
4144  byte adjust = 0;
4145  if ((f & H_FLAG) || ((getA() & 0xf) > 9)) adjust += 6;
4146  if ((f & C_FLAG) || (getA() > 0x99)) adjust += 0x60;
4147  if (f & N_FLAG) a -= adjust; else a += adjust;
4148  if (T::isR800()) {
4149  f &= C_FLAG | N_FLAG | X_FLAG | Y_FLAG;
4150  f |= ZSPTable[a];
4151  } else {
4152  f &= C_FLAG | N_FLAG;
4153  f |= ZSPXYTable[a];
4154  }
4155  f |= (getA() > 0x99) | ((getA() ^ a) & H_FLAG);
4156  setA(a);
4157  setF(f);
4158  return T::CC_DAA;
4159 }
4160 template<class T> int CPUCore<T>::neg() {
4161  // alternative: LUT word negTable[256]
4162  unsigned a = getA();
4163  unsigned res = -signed(a);
4164  byte f = ((res & 0x100) ? C_FLAG : 0) |
4165  N_FLAG |
4166  ((res ^ a) & H_FLAG) |
4167  ((a & res & 0x80) >> 5); // V_FLAG
4168  if (T::isR800()) {
4169  f |= ZSTable[res & 0xFF];
4170  f |= getF() & (X_FLAG | Y_FLAG);
4171  } else {
4172  f |= ZSXYTable[res & 0xFF];
4173  }
4174  setF(f);
4175  setA(res);
4176  return T::CC_NEG;
4177 }
4178 template<class T> int CPUCore<T>::scf() {
4179  byte f = C_FLAG;
4180  if (T::isR800()) {
4181  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | X_FLAG | Y_FLAG);
4182  } else {
4183  // only set X(Y) flag (don't reset if already set)
4184  if (isTurboR) {
4185  // Y flag is not changed on a turboR-Z80
4186  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG | Y_FLAG);
4187  f |= (getF() | getA()) & X_FLAG;
4188  } else {
4189  f |= getF() & (S_FLAG | Z_FLAG | P_FLAG);
4190  f |= (getF() | getA()) & (X_FLAG | Y_FLAG);
4191  }
4192  }
4193  setF(f);
4194  return T::CC_SCF;
4195 }
4196 
4197 template<class T> int CPUCore<T>::ex_af_af() {
4198  unsigned t = getAF2(); setAF2(getAF()); setAF(t);
4199  return T::CC_EX;
4200 }
4201 template<class T> int CPUCore<T>::ex_de_hl() {
4202  unsigned t = getDE(); setDE(getHL()); setHL(t);
4203  return T::CC_EX;
4204 }
4205 template<class T> int CPUCore<T>::exx() {
4206  unsigned t1 = getBC2(); setBC2(getBC()); setBC(t1);
4207  unsigned t2 = getDE2(); setDE2(getDE()); setDE(t2);
4208  unsigned t3 = getHL2(); setHL2(getHL()); setHL(t3);
4209  return T::CC_EX;
4210 }
4211 
4212 template<class T> int CPUCore<T>::di() {
4213  setIFF1(false);
4214  setIFF2(false);
4215  return T::CC_DI;
4216 }
4217 template<class T> int CPUCore<T>::ei() {
4218  setIFF1(true);
4219  setIFF2(true);
4220  setAfterEI(); // no ints directly after this instr
4221  setSlowInstructions();
4222  return T::CC_EI;
4223 }
4224 template<class T> int CPUCore<T>::halt() {
4225  setHALT(true);
4226  setSlowInstructions();
4227 
4228  if (!(getIFF1() || getIFF2())) {
4229  diHaltCallback.execute();
4230  }
4231  return T::CC_HALT;
4232 }
4233 template<class T> template<unsigned N> int CPUCore<T>::im_N() {
4234  setIM(N); return T::CC_IM;
4235 }
4236 
4237 // LD A,I/R
4238 template<class T> template<Reg8 REG> int CPUCore<T>::ld_a_IR() {
4239  setA(get8<REG>());
4240  byte f = getIFF2() ? V_FLAG : 0;
4241  if (T::isR800()) {
4242  f |= getF() & (C_FLAG | X_FLAG | Y_FLAG);
4243  f |= ZSTable[getA()];
4244  } else {
4245  f |= getF() & C_FLAG;
4246  f |= ZSXYTable[getA()];
4247  // see comment in the IRQ acceptance part of executeSlow().
4248  setAfterLDAI(); // only Z80 (not R800) has this quirk
4249  setSlowInstructions();
4250  }
4251  setF(f);
4252  return T::CC_LD_A_I;
4253 }
4254 
4255 // LD I/R,A
4256 template<class T> int CPUCore<T>::ld_r_a() {
4257  // This code sequence:
4258  // XOR A / LD R,A / LD A,R
4259  // gives A=2 for Z80, but A=1 for R800. The difference can possibly be
4260  // explained by a difference in the relative time between writing the
4261  // new value to the R register and increasing the R register per M1
4262  // cycle. Here we implemented the R800 behaviour by storing 'A-1' into
4263  // R, that's good enough for now.
4264  byte val = getA();
4265  if (T::isR800()) val -= 1;
4266  setR(val);
4267  return T::CC_LD_A_I;
4268 }
4269 template<class T> int CPUCore<T>::ld_i_a() {
4270  setI(getA());
4271  return T::CC_LD_A_I;
4272 }
4273 
4274 // MULUB A,r
4275 template<class T> template<Reg8 REG> int CPUCore<T>::mulub_a_R() {
4276  assert(T::isR800()); // this instruction is R800-only
4277  // Verified on real R800:
4278  // YHXN flags are unchanged
4279  // SV flags are reset
4280  // Z flag is set when result is zero
4281  // C flag is set when result doesn't fit in 8-bit
4282  setHL(unsigned(getA()) * get8<REG>());
4283  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4284  0 | // S_FLAG V_FLAG
4285  (getHL() ? 0 : Z_FLAG) |
4286  ((getHL() & 0xFF00) ? C_FLAG : 0));
4287  return T::CC_MULUB;
4288 }
4289 
4290 // MULUW HL,ss
4291 template<class T> template<Reg16 REG> int CPUCore<T>::muluw_hl_SS() {
4292  assert(T::isR800()); // this instruction is R800-only
4293  // Verified on real R800:
4294  // YHXN flags are unchanged
4295  // SV flags are reset
4296  // Z flag is set when result is zero
4297  // C flag is set when result doesn't fit in 16-bit
4298  unsigned res = unsigned(getHL()) * get16<REG>();
4299  setDE(res >> 16);
4300  setHL(res & 0xffff);
4301  setF((getF() & (N_FLAG | H_FLAG | X_FLAG | Y_FLAG)) |
4302  0 | // S_FLAG V_FLAG
4303  (res ? 0 : Z_FLAG) |
4304  ((res & 0xFFFF0000) ? C_FLAG : 0));
4305  return T::CC_MULUW;
4306 }
4307 
4308 
4309 // versions:
4310 // 1 -> initial version
4311 // 2 -> moved memptr from here to Z80TYPE (and not to R800TYPE)
4312 // 3 -> timing of the emulation changed (no changes in serialization)
4313 template<class T> template<typename Archive>
4314 void CPUCore<T>::serialize(Archive& ar, unsigned version)
4315 {
4316  T::serialize(ar, version);
4317  ar.serialize("regs", static_cast<CPURegs&>(*this));
4318  if (ar.versionBelow(version, 2)) {
4319  unsigned memptr = 0; // dummy value (avoid warning)
4320  ar.serialize("memptr", memptr);
4321  T::setMemPtr(memptr);
4322  }
4323 
4324  if (ar.isLoader()) {
4325  invalidateMemCache(0x0000, 0x10000);
4326  }
4327 
4328  // don't serialize
4329  // IRQStatus
4330  // NMIStatus, nmiEdge
4331  // slowInstructions
4332  // exitLoop
4333 
4334  if (T::isR800() && ar.versionBelow(version, 3)) {
4335  motherboard.getMSXCliComm().printWarning(
4336  "Loading an old savestate: the timing of the R800 "
4337  "emulation has changed. This may cause synchronization "
4338  "problems in replay.");
4339  }
4340 }
4341 
4342 // Force template instantiation
4343 template class CPUCore<Z80TYPE>;
4344 template class CPUCore<R800TYPE>;
4345 
4348 
4349 } // namespace openmsx
#define CASE(X)
void doReset(EmuTime::param time)
Reset the CPU.
Definition: CPUCore.cc:358
bool operator()(byte f) const
Definition: CPUCore.cc:258
bool operator()(byte f) const
Definition: CPUCore.cc:256
EmuTime::param getCurrentTime() const
Definition: CPUCore.cc:343
bool isM1Cycle(unsigned address) const
Definition: CPUCore.cc:484
size_type size() const
Definition: array_ref.hh:61
static const int CLOCK_FREQ
Definition: R800.hh:33
#define NEVER_INLINE
Definition: inline.hh:17
#define ALWAYS_INLINE
Definition: inline.hh:16
#define unlikely(x)
Definition: likely.hh:15
void exitCPULoopAsync()
Similar to exitCPULoopSync(), but this method may be called from any thread.
Definition: CPUCore.cc:423
void setFreq(unsigned freq)
Change the clock freq.
Definition: CPUCore.cc:545
void disasmCommand(Interpreter &interp, array_ref< TclObject > tokens, TclObject &result) const
Definition: CPUCore.cc:518
void lowerNMI()
Lowers the non-maskable interrupt count.
Definition: CPUCore.cc:478
bool operator()(byte f) const
Definition: CPUCore.cc:262
unsigned dasm(const MSXCPUInterface &interf, word pc, byte buf[4], std::string &dest, EmuTime::param time)
Disassemble.
Definition: Dasm.cc:18
bool operator()(byte f) const
Definition: CPUCore.cc:259
CPUCore(MSXMotherBoard &motherboard, const std::string &name, const BooleanSetting &traceSetting, TclCallback &diHaltCallback, EmuTime::param time)
Definition: CPUCore.cc:295
bool operator()(byte f) const
Definition: CPUCore.cc:257
bool operator()(byte) const
Definition: CPUCore.cc:264
void exitCPULoopSync()
Request to exit the main CPU emulation loop.
Definition: CPUCore.cc:428
void setNextSyncPoint(EmuTime::param time)
Definition: CPUCore.cc:502
#define NEXT
#define NEXT_STOP
This class implements a subset of the proposal for std::array_ref (proposed for the next c++ standard...
Definition: array_ref.hh:19
Thanks to enen for testing this on a real cartridge:
Definition: Autofire.cc:5
bool operator()(byte f) const
Definition: CPUCore.cc:260
unsigned char byte
8 bit unsigned integer
Definition: openmsx.hh:25
void raiseIRQ()
Raises the maskable interrupt count.
Definition: CPUCore.cc:450
void waitCycles(unsigned cycles)
Definition: CPUCore.cc:497
static const int CLOCK_FREQ
Definition: Z80.hh:17
bool operator()(byte f) const
Definition: CPUCore.cc:263
void execute(bool fastForward)
Definition: CPUCore.cc:2505
void addListElement(string_ref element)
Definition: TclObject.cc:120
void lowerIRQ()
Lowers the maskable interrupt count.
Definition: CPUCore.cc:459
#define INSTANTIATE_SERIALIZE_METHODS(CLASS)
Definition: serialize.hh:802
void wait(EmuTime::param time)
Definition: CPUCore.cc:490
#define NEXT_EI
void warp(EmuTime::param time)
Definition: CPUCore.cc:337
#define likely(x)
Definition: likely.hh:14
void serialize(Archive &ar, unsigned version)
Definition: CPUCore.cc:4314
size_t size(string_ref utf8)
bool operator()(byte f) const
Definition: CPUCore.cc:261
void serialize(Archive &ar, T &t, unsigned version)
void raiseNMI()
Raises the non-maskable interrupt count.
Definition: CPUCore.cc:465
static bool isMainThread()
Returns true when called from the main thread.
Definition: Thread.cc:19
void invalidateMemCache(unsigned start, unsigned size)
Definition: CPUCore.cc:348
unsigned short word
16 bit unsigned integer
Definition: openmsx.hh:28
#define UNREACHABLE
Definition: unreachable.hh:35